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-rw-r--r--src/mem/Bus.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 05033d382..12657e177 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -49,7 +49,7 @@ class BaseBus(MemObject):
master = VectorMasterPort("vector port for connecting slaves")
clock = Param.Clock("1GHz", "bus clock speed")
header_cycles = Param.Int(1, "cycles of overhead per transaction")
- width = Param.Int(64, "bus width (bytes)")
+ width = Param.Int(8, "bus width (bytes)")
block_size = Param.Int(64, "The default block size if not set by " \
"any connected module")