diff options
Diffstat (limited to 'src/mem')
34 files changed, 53 insertions, 0 deletions
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py index ce3f04c49..f96ca5b78 100644 --- a/src/mem/AbstractMemory.py +++ b/src/mem/AbstractMemory.py @@ -45,6 +45,7 @@ from MemObject import MemObject class AbstractMemory(MemObject): type = 'AbstractMemory' abstract = True + cxx_header = "mem/abstract_mem.hh" range = Param.AddrRange(AddrRange('128MB'), "Address range") null = Param.Bool(False, "Do not store data, always return zero") zero = Param.Bool(False, "Initialize memory with zeros") diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py index 2b999ee92..f6e943ed1 100644 --- a/src/mem/AddrMapper.py +++ b/src/mem/AddrMapper.py @@ -46,6 +46,7 @@ from MemObject import MemObject # currently not modified. class AddrMapper(MemObject): type = 'AddrMapper' + cxx_header = 'mem/addr_mapper.hh' abstract = True # one port in each direction @@ -58,6 +59,7 @@ class AddrMapper(MemObject): # (original and remapped), only with an offset. class RangeAddrMapper(AddrMapper): type = 'RangeAddrMapper' + cxx_header = 'mem/addr_mapper.hh' # These two vectors should be the exact same length and each range # should be the exact same size. Each range in original_ranges is diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py index 62dfb7351..5f2cc9f40 100644 --- a/src/mem/Bridge.py +++ b/src/mem/Bridge.py @@ -44,6 +44,7 @@ from MemObject import MemObject class Bridge(MemObject): type = 'Bridge' + cxx_header = "mem/bridge.hh" slave = SlavePort('Slave port') master = MasterPort('Master port') req_size = Param.Int(16, "The number of requests to buffer") diff --git a/src/mem/Bus.py b/src/mem/Bus.py index 45b1f1b0a..4637b0ebc 100644 --- a/src/mem/Bus.py +++ b/src/mem/Bus.py @@ -45,6 +45,7 @@ from m5.params import * class BaseBus(MemObject): type = 'BaseBus' abstract = True + cxx_header = "mem/bus.hh" slave = VectorSlavePort("vector port for connecting masters") master = VectorMasterPort("vector port for connecting slaves") header_cycles = Param.Cycles(1, "cycles of overhead per transaction") @@ -66,6 +67,8 @@ class BaseBus(MemObject): class NoncoherentBus(BaseBus): type = 'NoncoherentBus' + cxx_header = "mem/noncoherent_bus.hh" class CoherentBus(BaseBus): type = 'CoherentBus' + cxx_header = "mem/coherent_bus.hh" diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index 3621942d9..a34a57db4 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -43,6 +43,7 @@ from MemObject import MemObject # with periodic dumping and resetting of stats using schedStatEvent class CommMonitor(MemObject): type = 'CommMonitor' + cxx_header = "mem/comm_monitor.hh" # one port in each direction master = MasterPort("Master port") diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py index 0f33cc0bf..0827218aa 100644 --- a/src/mem/MemObject.py +++ b/src/mem/MemObject.py @@ -31,3 +31,4 @@ from ClockedObject import ClockedObject class MemObject(ClockedObject): type = 'MemObject' abstract = True + cxx_header = "mem/mem_object.hh" diff --git a/src/mem/SimpleDRAM.py b/src/mem/SimpleDRAM.py index c87425610..3211f576a 100644 --- a/src/mem/SimpleDRAM.py +++ b/src/mem/SimpleDRAM.py @@ -57,6 +57,7 @@ class PageManage(Enum): vals = ['open', 'close'] # itself. class SimpleDRAM(AbstractMemory): type = 'SimpleDRAM' + cxx_header = "mem/simple_dram.hh" # single-ported on the system interface side, instantiate with a # bus in front of the controller for multiple ports diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py index 9361b45d8..0cf6dece3 100644 --- a/src/mem/SimpleMemory.py +++ b/src/mem/SimpleMemory.py @@ -44,6 +44,7 @@ from AbstractMemory import * class SimpleMemory(AbstractMemory): type = 'SimpleMemory' + cxx_header = "mem/simple_mem.hh" port = SlavePort("Slave ports") latency = Param.Latency('30ns', "Request to response latency") latency_var = Param.Latency('0ns', "Request to response latency variance") diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py index 6fe73a9c2..fe0d9ceb0 100644 --- a/src/mem/cache/BaseCache.py +++ b/src/mem/cache/BaseCache.py @@ -46,6 +46,7 @@ from Prefetcher import BasePrefetcher class BaseCache(MemObject): type = 'BaseCache' + cxx_header = "mem/cache/base.hh" assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") hit_latency = Param.Cycles("The hit latency for this cache") diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index e590410ae..af67f40b6 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -45,6 +45,7 @@ from m5.proxy import * class BasePrefetcher(ClockedObject): type = 'BasePrefetcher' abstract = True + cxx_header = "mem/cache/prefetch/base.hh" size = Param.Int(100, "Number of entries in the hardware prefetch queue") cross_pages = Param.Bool(False, @@ -63,14 +64,17 @@ class BasePrefetcher(ClockedObject): class GHBPrefetcher(BasePrefetcher): type = 'GHBPrefetcher' cxx_class = 'GHBPrefetcher' + cxx_header = "mem/cache/prefetch/ghb.hh" class StridePrefetcher(BasePrefetcher): type = 'StridePrefetcher' cxx_class = 'StridePrefetcher' + cxx_header = "mem/cache/prefetch/stride.hh" class TaggedPrefetcher(BasePrefetcher): type = 'TaggedPrefetcher' cxx_class = 'TaggedPrefetcher' + cxx_header = "mem/cache/prefetch/tagged.hh" diff --git a/src/mem/cache/tags/iic_repl/Repl.py b/src/mem/cache/tags/iic_repl/Repl.py index 4c333e897..577eb8fed 100644 --- a/src/mem/cache/tags/iic_repl/Repl.py +++ b/src/mem/cache/tags/iic_repl/Repl.py @@ -31,9 +31,11 @@ from m5.params import * class Repl(SimObject): type = 'Repl' abstract = True + cxx_header = "mem/cache/tags/iic_repl/repl.hh" class GenRepl(Repl): type = 'GenRepl' + cxx_header = "mem/cache/tags/iic_repl/gen.hh" fresh_res = Param.Int("Fresh pool residency time") num_pools = Param.Int("Number of priority pools") pool_res = Param.Int("Pool residency time") diff --git a/src/mem/ruby/network/BasicLink.py b/src/mem/ruby/network/BasicLink.py index f73f5d977..841208578 100644 --- a/src/mem/ruby/network/BasicLink.py +++ b/src/mem/ruby/network/BasicLink.py @@ -32,6 +32,7 @@ from m5.SimObject import SimObject class BasicLink(SimObject): type = 'BasicLink' + cxx_header = "mem/ruby/network/BasicLink.hh" link_id = Param.Int("ID in relation to other links") latency = Param.Int(1, "latency") # The following banwidth factor does not translate to the same value for @@ -43,12 +44,14 @@ class BasicLink(SimObject): class BasicExtLink(BasicLink): type = 'BasicExtLink' + cxx_header = "mem/ruby/network/BasicLink.hh" ext_node = Param.RubyController("External node") int_node = Param.BasicRouter("ID of internal node") bandwidth_factor = 16 class BasicIntLink(BasicLink): type = 'BasicIntLink' + cxx_header = "mem/ruby/network/BasicLink.hh" node_a = Param.BasicRouter("Router on one end") node_b = Param.BasicRouter("Router on other end") bandwidth_factor = 16 diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py index 0ff41c33c..0c8e5cb54 100644 --- a/src/mem/ruby/network/BasicRouter.py +++ b/src/mem/ruby/network/BasicRouter.py @@ -32,4 +32,5 @@ from m5.SimObject import SimObject class BasicRouter(SimObject): type = 'BasicRouter' + cxx_header = "mem/ruby/network/BasicRouter.hh" router_id = Param.Int("ID in relation to other routers") diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py index 9642b046e..4bc35b30c 100644 --- a/src/mem/ruby/network/Network.py +++ b/src/mem/ruby/network/Network.py @@ -33,6 +33,7 @@ from BasicLink import BasicLink class Topology(SimObject): type = 'Topology' + cxx_header = "mem/ruby/network/Topology.hh" description = Param.String("Not Specified", "the name of the imported topology module") ext_links = VectorParam.BasicExtLink("Links to external nodes") @@ -44,6 +45,7 @@ class Topology(SimObject): class RubyNetwork(SimObject): type = 'RubyNetwork' cxx_class = 'Network' + cxx_header = "mem/ruby/network/Network.hh" abstract = True number_of_virtual_networks = Param.Int(10, ""); topology = Param.Topology(""); diff --git a/src/mem/ruby/network/fault_model/FaultModel.py b/src/mem/ruby/network/fault_model/FaultModel.py index 5117491f2..b1532150b 100644 --- a/src/mem/ruby/network/fault_model/FaultModel.py +++ b/src/mem/ruby/network/fault_model/FaultModel.py @@ -39,6 +39,7 @@ from m5.SimObject import SimObject class FaultModel(SimObject): type = 'FaultModel' cxx_class = 'FaultModel' + cxx_header = "mem/ruby/network/fault_model/FaultModel.hh" baseline_fault_vector_database = VectorParam.Float([ 5, 40, 0.080892, 0.109175, 0.018864, 0.130408, 0.059724, 0.077571, 0.034830, 0.083430, 0.067500, 0.121500, diff --git a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py index 2431db203..0bcb0484d 100644 --- a/src/mem/ruby/network/garnet/BaseGarnetNetwork.py +++ b/src/mem/ruby/network/garnet/BaseGarnetNetwork.py @@ -33,6 +33,7 @@ from Network import RubyNetwork class BaseGarnetNetwork(RubyNetwork): type = 'BaseGarnetNetwork' + cxx_header = "mem/ruby/network/garnet/BaseGarnetNetwork.hh" abstract = True ni_flit_size = Param.Int(16, "network interface flit size in bytes") vcs_per_vnet = Param.Int(4, "virtual channels per virtual network"); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py index 1fb7e0b7b..e5de4ecaf 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.py @@ -35,6 +35,7 @@ from BasicLink import BasicIntLink, BasicExtLink class NetworkLink_d(SimObject): type = 'NetworkLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh" link_id = Param.Int(Parent.link_id, "link id") link_latency = Param.Int(Parent.latency, "link latency") vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, @@ -46,10 +47,12 @@ class NetworkLink_d(SimObject): class CreditLink_d(NetworkLink_d): type = 'CreditLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/CreditLink_d.hh" # Interior fixed pipeline links between routers class GarnetIntLink_d(BasicIntLink): type = 'GarnetIntLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction nls = [] @@ -69,6 +72,7 @@ class GarnetIntLink_d(BasicIntLink): # Exterior fixed pipeline links between a router and a controller class GarnetExtLink_d(BasicExtLink): type = 'GarnetExtLink_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetLink_d.hh" # The detailed fixed pipeline bi-directional link include two main # forward links and two backward flow-control links, one per direction nls = [] diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py index a3a00525d..6ebf94e04 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.py @@ -33,5 +33,6 @@ from BaseGarnetNetwork import BaseGarnetNetwork class GarnetNetwork_d(BaseGarnetNetwork): type = 'GarnetNetwork_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh" buffers_per_data_vc = Param.Int(4, "buffers per data virtual channel"); buffers_per_ctrl_vc = Param.Int(1, "buffers per ctrl virtual channel"); diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py index b2a01fb46..cd009a807 100644 --- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py +++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetRouter_d.py @@ -35,6 +35,7 @@ from BasicRouter import BasicRouter class GarnetRouter_d(BasicRouter): type = 'GarnetRouter_d' cxx_class = 'Router_d' + cxx_header = "mem/ruby/network/garnet/fixed-pipeline/Router_d.hh" vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py index 591ab4beb..d5b55c1ec 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetLink.py @@ -35,6 +35,7 @@ from BasicLink import BasicIntLink, BasicExtLink class NetworkLink(SimObject): type = 'NetworkLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh" link_id = Param.Int(Parent.link_id, "link id") link_latency = Param.Int(Parent.latency, "link latency") vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, @@ -47,6 +48,7 @@ class NetworkLink(SimObject): # Interior fixed pipeline links between routers class GarnetIntLink(BasicIntLink): type = 'GarnetIntLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh" # The flexible pipeline bi-directional link only include two main # forward links and no backward flow-control links nls = [] @@ -59,6 +61,7 @@ class GarnetIntLink(BasicIntLink): # Exterior fixed pipeline links between a router and a controller class GarnetExtLink(BasicExtLink): type = 'GarnetExtLink' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetLink.hh" # The flexible pipeline bi-directional link only include two main # forward links and no backward flow-control links nls = [] diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py index 7ad61a5ce..28f81d732 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.py @@ -33,6 +33,7 @@ from BaseGarnetNetwork import BaseGarnetNetwork class GarnetNetwork(BaseGarnetNetwork): type = 'GarnetNetwork' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh" buffer_size = Param.Int(0, "default buffer size; 0 indicates infinite buffering"); number_of_pipe_stages = Param.Int(4, "router pipeline stages"); diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py index a39348c46..22d8c8670 100644 --- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py +++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetRouter.py @@ -35,6 +35,7 @@ from BasicRouter import BasicRouter class GarnetRouter(BasicRouter): type = 'GarnetRouter' cxx_class = 'Router' + cxx_header = "mem/ruby/network/garnet/flexible-pipeline/Router.hh" vcs_per_vnet = Param.Int(Parent.vcs_per_vnet, "virtual channels per virtual network") virt_nets = Param.Int(Parent.number_of_virtual_networks, diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py index 55b21562e..716a21eec 100644 --- a/src/mem/ruby/network/simple/SimpleLink.py +++ b/src/mem/ruby/network/simple/SimpleLink.py @@ -34,6 +34,8 @@ from BasicLink import BasicIntLink, BasicExtLink class SimpleExtLink(BasicExtLink): type = 'SimpleExtLink' + cxx_header = "mem/ruby/network/simple/SimpleLink.hh" class SimpleIntLink(BasicIntLink): type = 'SimpleIntLink' + cxx_header = "mem/ruby/network/simple/SimpleLink.hh" diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py index 0603546ce..217dc20ec 100644 --- a/src/mem/ruby/network/simple/SimpleNetwork.py +++ b/src/mem/ruby/network/simple/SimpleNetwork.py @@ -34,6 +34,7 @@ from BasicRouter import BasicRouter class SimpleNetwork(RubyNetwork): type = 'SimpleNetwork' + cxx_header = "mem/ruby/network/simple/SimpleNetwork.hh" buffer_size = Param.Int(0, "default buffer size; 0 indicates infinite buffering"); endpoint_bandwidth = Param.Int(1000, "bandwidth adjustment factor"); diff --git a/src/mem/ruby/profiler/Profiler.py b/src/mem/ruby/profiler/Profiler.py index 3521911c2..0bb1bbc3d 100644 --- a/src/mem/ruby/profiler/Profiler.py +++ b/src/mem/ruby/profiler/Profiler.py @@ -33,6 +33,7 @@ from m5.SimObject import SimObject class RubyProfiler(SimObject): type = 'RubyProfiler' cxx_class = 'Profiler' + cxx_header = "mem/ruby/profiler/Profiler.hh" hot_lines = Param.Bool(False, "") all_instructions = Param.Bool(False, "") num_of_sequencers = Param.Int("") diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py index 44e08ecdc..9787b5ce7 100644 --- a/src/mem/ruby/slicc_interface/Controller.py +++ b/src/mem/ruby/slicc_interface/Controller.py @@ -33,6 +33,7 @@ from m5.SimObject import SimObject class RubyController(SimObject): type = 'RubyController' cxx_class = 'AbstractController' + cxx_header = "mem/ruby/slicc_interface/AbstractController.hh" abstract = True version = Param.Int("") cntrl_id = Param.Int("") diff --git a/src/mem/ruby/system/Cache.py b/src/mem/ruby/system/Cache.py index 57326c3c6..4b0269822 100644 --- a/src/mem/ruby/system/Cache.py +++ b/src/mem/ruby/system/Cache.py @@ -34,6 +34,7 @@ from Controller import RubyController class RubyCache(SimObject): type = 'RubyCache' cxx_class = 'CacheMemory' + cxx_header = "mem/ruby/system/CacheMemory.hh" size = Param.MemorySize("capacity in bytes"); latency = Param.Int(""); assoc = Param.Int(""); diff --git a/src/mem/ruby/system/DirectoryMemory.py b/src/mem/ruby/system/DirectoryMemory.py index d3b6bc591..ac4dd5934 100644 --- a/src/mem/ruby/system/DirectoryMemory.py +++ b/src/mem/ruby/system/DirectoryMemory.py @@ -34,6 +34,7 @@ from m5.SimObject import SimObject class RubyDirectoryMemory(SimObject): type = 'RubyDirectoryMemory' cxx_class = 'DirectoryMemory' + cxx_header = "mem/ruby/system/DirectoryMemory.hh" version = Param.Int(0, "") size = Param.MemorySize("1GB", "capacity in bytes") use_map = Param.Bool(False, "enable sparse memory") diff --git a/src/mem/ruby/system/MemoryControl.py b/src/mem/ruby/system/MemoryControl.py index 09c940fee..ad18efec5 100644 --- a/src/mem/ruby/system/MemoryControl.py +++ b/src/mem/ruby/system/MemoryControl.py @@ -34,5 +34,6 @@ class MemoryControl(ClockedObject): abstract = True type = 'MemoryControl' cxx_class = 'MemoryControl' + cxx_header = "mem/ruby/system/MemoryControl.hh" version = Param.Int(""); ruby_system = Param.RubySystem("") diff --git a/src/mem/ruby/system/RubyMemoryControl.py b/src/mem/ruby/system/RubyMemoryControl.py index e65b6f5cc..7764938d3 100644 --- a/src/mem/ruby/system/RubyMemoryControl.py +++ b/src/mem/ruby/system/RubyMemoryControl.py @@ -34,6 +34,7 @@ from MemoryControl import MemoryControl class RubyMemoryControl(MemoryControl): type = 'RubyMemoryControl' cxx_class = 'RubyMemoryControl' + cxx_header = "mem/ruby/system/RubyMemoryControl.hh" version = Param.Int(""); # Override the default clock diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py index c9d2e96ac..b1f625723 100644 --- a/src/mem/ruby/system/RubySystem.py +++ b/src/mem/ruby/system/RubySystem.py @@ -32,6 +32,7 @@ from ClockedObject import ClockedObject class RubySystem(ClockedObject): type = 'RubySystem' + cxx_header = "mem/ruby/system/System.hh" random_seed = Param.Int(1234, "random seed used by the simulation"); randomization = Param.Bool(False, "insert random delays on message enqueue times"); diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py index deef6e714..9b243a8b9 100644 --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -34,6 +34,7 @@ from MemObject import MemObject class RubyPort(MemObject): type = 'RubyPort' abstract = True + cxx_header = "mem/ruby/system/RubyPort.hh" slave = VectorSlavePort("CPU slave port") master = VectorMasterPort("CPU master port") version = Param.Int(0, "") @@ -50,10 +51,12 @@ class RubyPort(MemObject): class RubyPortProxy(RubyPort): type = 'RubyPortProxy' + cxx_header = "mem/ruby/system/RubyPortProxy.hh" class RubySequencer(RubyPort): type = 'RubySequencer' cxx_class = 'Sequencer' + cxx_header = "mem/ruby/system/Sequencer.hh" icache = Param.RubyCache("") dcache = Param.RubyCache("") max_outstanding_requests = Param.Int(16, @@ -63,3 +66,4 @@ class RubySequencer(RubyPort): class DMASequencer(RubyPort): type = 'DMASequencer' + cxx_header = "mem/ruby/system/DMASequencer.hh" diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py index bca19b4df..f48ab1f95 100644 --- a/src/mem/ruby/system/WireBuffer.py +++ b/src/mem/ruby/system/WireBuffer.py @@ -32,3 +32,4 @@ from m5.SimObject import SimObject class RubyWireBuffer(SimObject): type = 'RubyWireBuffer' cxx_class = 'WireBuffer' + cxx_header = "mem/ruby/system/WireBuffer.hh" diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py index 427dbf700..f07e521d3 100644 --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -185,6 +185,7 @@ from Controller import RubyController class $py_ident(RubyController): type = '$py_ident' + cxx_header = 'mem/protocol/${c_ident}.hh' ''') code.indent() for param in self.config_parameters: |