diff options
Diffstat (limited to 'src/mem')
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L1cache.sm | 14 | ||||
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-L2cache.sm | 10 | ||||
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-dma.sm | 36 | ||||
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-mem.sm | 79 | ||||
| -rw-r--r-- | src/mem/protocol/MESI_CMP_directory-msg.sm | 68 | ||||
| -rw-r--r-- | src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb | 2 | ||||
| -rw-r--r-- | src/mem/slicc/symbols/StateMachine.cc | 96 |
7 files changed, 61 insertions, 244 deletions
diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm index 32669190f..8c8bbfaa6 100644 --- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm @@ -27,12 +27,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/* - * $Id: MSI_MOSI_CMP_directory-L1cache.sm 1.10 05/01/19 15:55:40-06:00 beckmann@s0-28.cs.wisc.edu $ - * - */ - - machine(L1Cache, "MSI Directory L1 Cache CMP") : int l1_request_latency, int l1_response_latency, @@ -47,15 +41,15 @@ machine(L1Cache, "MSI Directory L1 Cache CMP") // a local L1 -> this L2 bank, currently ordered with directory forwarded requests MessageBuffer requestFromL1Cache, network="To", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank - MessageBuffer responseFromL1Cache, network="To", virtual_network="3", ordered="false"; - MessageBuffer unblockFromL1Cache, network="To", virtual_network="4", ordered="false"; + MessageBuffer responseFromL1Cache, network="To", virtual_network="1", ordered="false"; + MessageBuffer unblockFromL1Cache, network="To", virtual_network="2", ordered="false"; // To this node's L1 cache FROM the network // a L2 bank -> this L1 - MessageBuffer requestToL1Cache, network="From", virtual_network="1", ordered="false"; + MessageBuffer requestToL1Cache, network="From", virtual_network="0", ordered="false"; // a L2 bank -> this L1 - MessageBuffer responseToL1Cache, network="From", virtual_network="3", ordered="false"; + MessageBuffer responseToL1Cache, network="From", virtual_network="1", ordered="false"; // STATES enumeration(State, desc="Cache states", default="L1Cache_State_I") { diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm index 6439e4fb3..b82d77ddb 100644 --- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm @@ -40,14 +40,14 @@ machine(L2Cache, "MESI Directory L2 Cache CMP") // L2 BANK QUEUES // From local bank of L2 cache TO the network - MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="2", ordered="false"; // this L2 bank -> Memory - MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 - MessageBuffer responseFromL2Cache, network="To", virtual_network="3", ordered="false"; // this L2 bank -> a local L1 || Memory + MessageBuffer DirRequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> Memory + MessageBuffer L1RequestFromL2Cache, network="To", virtual_network="0", ordered="false"; // this L2 bank -> a local L1 + MessageBuffer responseFromL2Cache, network="To", virtual_network="1", ordered="false"; // this L2 bank -> a local L1 || Memory // FROM the network to this local bank of L2 cache - MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank + MessageBuffer unblockToL2Cache, network="From", virtual_network="2", ordered="false"; // a local L1 || Memory -> this L2 bank MessageBuffer L1RequestToL2Cache, network="From", virtual_network="0", ordered="false"; // a local L1 -> this L2 bank - MessageBuffer responseToL2Cache, network="From", virtual_network="3", ordered="false"; // a local L1 || Memory -> this L2 bank + MessageBuffer responseToL2Cache, network="From", virtual_network="1", ordered="false"; // a local L1 || Memory -> this L2 bank // MessageBuffer unblockToL2Cache, network="From", virtual_network="4", ordered="false"; // a local L1 || Memory -> this L2 bank // STATES diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm index 191df5dfa..143c465ef 100644 --- a/src/mem/protocol/MESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MESI_CMP_directory-dma.sm @@ -3,8 +3,8 @@ machine(DMA, "DMA Controller") : int request_latency { - MessageBuffer responseFromDir, network="From", virtual_network="6", ordered="true", no_vector="true"; - MessageBuffer reqToDirectory, network="To", virtual_network="7", ordered="false", no_vector="true"; + MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", no_vector="true"; + MessageBuffer reqToDirectory, network="To", virtual_network="0", ordered="false", no_vector="true"; enumeration(State, desc="DMA states", default="DMA_State_READY") { READY, desc="Ready to accept a new request"; @@ -51,13 +51,13 @@ machine(DMA, "DMA Controller") } } - in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") { + in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") { if (dmaResponseQueue_in.isReady()) { - peek( dmaResponseQueue_in, DMAResponseMsg) { - if (in_msg.Type == DMAResponseType:ACK) { - trigger(Event:Ack, in_msg.LineAddress); - } else if (in_msg.Type == DMAResponseType:DATA) { - trigger(Event:Data, in_msg.LineAddress); + peek( dmaResponseQueue_in, ResponseMsg) { + if (in_msg.Type == CoherenceResponseType:ACK) { + trigger(Event:Ack, makeLineAddress(in_msg.Address)); + } else if (in_msg.Type == CoherenceResponseType:DATA) { + trigger(Event:Data, makeLineAddress(in_msg.Address)); } else { error("Invalid response type"); } @@ -67,10 +67,9 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { - out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; - out_msg.Type := DMARequestType:READ; + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := in_msg.PhysicalAddress; + out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -81,10 +80,9 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { - enqueue(reqToDirectory_out, DMARequestMsg, latency=request_latency) { - out_msg.PhysicalAddress := in_msg.PhysicalAddress; - out_msg.LineAddress := in_msg.LineAddress; - out_msg.Type := DMARequestType:WRITE; + enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { + out_msg.Address := in_msg.PhysicalAddress; + out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; out_msg.Destination.add(map_Address_to_Directory(address)); @@ -94,13 +92,11 @@ machine(DMA, "DMA Controller") } action(a_ackCallback, "a", desc="Notify dma controller that write request completed") { - peek (dmaResponseQueue_in, DMAResponseMsg) { - dma_sequencer.ackCallback(); - } + dma_sequencer.ackCallback(); } action(d_dataCallback, "d", desc="Write data to dma sequencer") { - peek (dmaResponseQueue_in, DMAResponseMsg) { + peek (dmaResponseQueue_in, ResponseMsg) { dma_sequencer.dataCallback(in_msg.DataBlk); } } diff --git a/src/mem/protocol/MESI_CMP_directory-mem.sm b/src/mem/protocol/MESI_CMP_directory-mem.sm index f5a2e431b..82902e8af 100644 --- a/src/mem/protocol/MESI_CMP_directory-mem.sm +++ b/src/mem/protocol/MESI_CMP_directory-mem.sm @@ -40,13 +40,11 @@ machine(Directory, "MESI_CMP_filter_directory protocol") int directory_latency { - MessageBuffer requestToDir, network="From", virtual_network="2", ordered="false"; - MessageBuffer responseToDir, network="From", virtual_network="3", ordered="false"; - MessageBuffer responseFromDir, network="To", virtual_network="3", ordered="false"; - - MessageBuffer dmaRequestFromDir, network="To", virtual_network="6", ordered="true"; - MessageBuffer dmaRequestToDir, network="From", virtual_network="7", ordered="true"; + MessageBuffer requestToDir, network="From", virtual_network="0", ordered="false"; + MessageBuffer responseToDir, network="From", virtual_network="1", ordered="false"; + MessageBuffer requestFromDir, network="To", virtual_network="0", ordered="false"; + MessageBuffer responseFromDir, network="To", virtual_network="1", ordered="false"; // STATES enumeration(State, desc="Directory states", default="Directory_State_I") { @@ -167,32 +165,19 @@ machine(Directory, "MESI_CMP_filter_directory protocol") // ** OUT_PORTS ** out_port(responseNetwork_out, ResponseMsg, responseFromDir); out_port(memQueue_out, MemoryMsg, memBuffer); - out_port(dmaResponseNetwork_out, DMAResponseMsg, dmaRequestFromDir); // ** IN_PORTS ** -//added by SS for dma - in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) { - if (dmaRequestQueue_in.isReady()) { - peek(dmaRequestQueue_in, DMARequestMsg) { - if (in_msg.Type == DMARequestType:READ) { - trigger(Event:DMA_READ, in_msg.LineAddress); - } else if (in_msg.Type == DMARequestType:WRITE) { - trigger(Event:DMA_WRITE, in_msg.LineAddress); - } else { - error("Invalid message"); - } - } - } - } - - in_port(requestNetwork_in, RequestMsg, requestToDir) { if (requestNetwork_in.isReady()) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (isGETRequest(in_msg.Type)) { trigger(Event:Fetch, in_msg.Address); + } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { + trigger(Event:DMA_READ, makeLineAddress(in_msg.Address)); + } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) { + trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address)); } else { DEBUG_EXPR(in_msg); error("Invalid message"); @@ -328,7 +313,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } //added by SS for dma action(qf_queueMemoryFetchRequestDMA, "qfd", desc="Queue off-chip fetch request") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_READ; @@ -342,14 +327,14 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") { - dmaRequestQueue_in.dequeue(); + requestNetwork_in.dequeue(); } action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { peek(memQueue_in, MemoryMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:DATA; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Response_Data; @@ -358,15 +343,13 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } action(dw_writeDMAData, "dw", desc="DMA Write data to memory") { - peek(dmaRequestQueue_in, DMARequestMsg) { - //directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len); - - directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.PhysicalAddress), in_msg.Len); + peek(requestNetwork_in, RequestMsg) { + directory[address].DataBlk.copyPartial(in_msg.DataBlk, addressOffset(in_msg.Address), in_msg.Len); } } action(qw_queueMemoryWBRequest_partial, "qwp", desc="Queue off-chip writeback request") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(memQueue_out, MemoryMsg, latency=to_mem_ctrl_latency) { out_msg.Address := address; out_msg.Type := MemoryRequestType:MEMORY_WB; @@ -384,9 +367,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:ACK; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:ACK; out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Writeback_Control; } @@ -397,7 +380,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") { - dmaRequestQueue_in.recycle(); + requestNetwork_in.recycle(); } @@ -410,12 +393,12 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { enqueue(responseNetwork_out, ResponseMsg, latency=directory_latency) { out_msg.Address := address; out_msg.Type := CoherenceResponseType:INV; out_msg.Sender := machineID; - out_msg.Destination := directory[in_msg.PhysicalAddress].Owner; + out_msg.Destination := directory[address].Owner; out_msg.MessageSize := MessageSizeType:Response_Control; } } @@ -424,9 +407,9 @@ machine(Directory, "MESI_CMP_filter_directory protocol") action(drp_sendDMAData, "drp", desc="Send Data to DMA controller from incoming PUTX") { peek(responseNetwork_in, ResponseMsg) { - enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency=to_mem_ctrl_latency) { - out_msg.PhysicalAddress := address; - out_msg.Type := DMAResponseType:DATA; + enqueue(responseNetwork_out, ResponseMsg, latency=to_mem_ctrl_latency) { + out_msg.Address := address; + out_msg.Type := CoherenceResponseType:DATA; out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be out_msg.Destination.add(map_Address_to_DMA(address)); out_msg.MessageSize := MessageSizeType:Response_Data; @@ -439,10 +422,10 @@ machine(Directory, "MESI_CMP_filter_directory protocol") } action(v_allocateTBE, "v", desc="Allocate TBE") { - peek(dmaRequestQueue_in, DMARequestMsg) { + peek(requestNetwork_in, RequestMsg) { TBEs.allocate(address); TBEs[address].DataBlk := in_msg.DataBlk; - TBEs[address].PhysicalAddress := in_msg.PhysicalAddress; + TBEs[address].PhysicalAddress := in_msg.Address; TBEs[address].Len := in_msg.Len; } } @@ -514,7 +497,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") //added by SS for dma support transition(I, DMA_READ, ID) { qf_queueMemoryFetchRequestDMA; - p_popIncomingDMARequestQueue; + j_popIncomingRequestQueue; } transition(ID, Memory_Data, I) { @@ -525,7 +508,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") transition(I, DMA_WRITE, ID_W) { dw_writeDMAData; qw_queueMemoryWBRequest_partial; - p_popIncomingDMARequestQueue; + j_popIncomingRequestQueue; } transition(ID_W, Memory_Ack, I) { @@ -544,7 +527,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") transition(M, DMA_READ, M_DRD) { inv_sendCacheInvalidate; - p_popIncomingDMARequestQueue; + j_popIncomingRequestQueue; } transition(M_DRD, Data, M_DRDI) { @@ -563,7 +546,7 @@ machine(Directory, "MESI_CMP_filter_directory protocol") transition(M, DMA_WRITE, M_DWR) { v_allocateTBE; inv_sendCacheInvalidate; - p_popIncomingDMARequestQueue; + j_popIncomingRequestQueue; } transition(M_DWR, Data, M_DWRI) { diff --git a/src/mem/protocol/MESI_CMP_directory-msg.sm b/src/mem/protocol/MESI_CMP_directory-msg.sm index 15934e6b2..74c1e56f0 100644 --- a/src/mem/protocol/MESI_CMP_directory-msg.sm +++ b/src/mem/protocol/MESI_CMP_directory-msg.sm @@ -70,7 +70,8 @@ enumeration(CoherenceRequestType, desc="...") { WB_NACK, desc="Writeback neg. ack"; FWD, desc="Generic FWD"; - + DMA_READ, desc="DMA Read"; + DMA_WRITE, desc="DMA Write"; } // CoherenceResponseType @@ -95,6 +96,7 @@ structure(RequestMsg, desc="...", interface="NetworkMessage") { NetDest Destination, desc="What components receive the request, includes MachineType and num"; MessageSizeType MessageSize, desc="size category of the message"; DataBlock DataBlk, desc="Data for the cache line (if PUTX)"; + int Len; bool Dirty, default="false", desc="Dirty bit"; PrefetchBit Prefetch, desc="Is this a prefetch request"; } @@ -111,68 +113,4 @@ structure(ResponseMsg, desc="...", interface="NetworkMessage") { MessageSizeType MessageSize, desc="size category of the message"; } -enumeration(DMARequestType, desc="...", default="DMARequestType_NULL") { - READ, desc="Memory Read"; - WRITE, desc="Memory Write"; - NULL, desc="Invalid"; -} - -enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") { - DATA, desc="DATA read"; - ACK, desc="ACK write"; - NULL, desc="Invalid"; -} - -structure(DMARequestMsg, desc="...", interface="NetworkMessage") { - DMARequestType Type, desc="Request type (read/write)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; - NetDest Destination, desc="Destination"; - DataBlock DataBlk, desc="DataBlk attached to this request"; - int Offset, desc="The offset into the datablock"; - int Len, desc="The length of the request"; - MessageSizeType MessageSize, desc="size category of the message"; -} - -structure(DMAResponseMsg, desc="...", interface="NetworkMessage") { - DMAResponseType Type, desc="Response type (DATA/ACK)"; - Address PhysicalAddress, desc="Physical address for this request"; - Address LineAddress, desc="Line address for this request"; - NetDest Destination, desc="Destination"; - DataBlock DataBlk, desc="DataBlk attached to this request"; - MessageSizeType MessageSize, desc="size category of the message"; -} - - - -/* -GenericRequestType convertToGenericType(CoherenceRequestType type) { - if(type == CoherenceRequestType:PUTX) { - return GenericRequestType:PUTX; - } else if(type == CoherenceRequestType:GETS) { - return GenericRequestType:GETS; - } else if(type == CoherenceRequestType:GET_INSTR) { - return GenericRequestType:GET_INSTR; - } else if(type == CoherenceRequestType:GETX) { - return GenericRequestType:GETX; - } else if(type == CoherenceRequestType:UPGRADE) { - return GenericRequestType:UPGRADE; - } else if(type == CoherenceRequestType:PUTS) { - return GenericRequestType:PUTS; - } else if(type == CoherenceRequestType:INV) { - return GenericRequestType:INV; - } else if(type == CoherenceRequestType:INV_S) { - return GenericRequestType:INV_S; - } else if(type == CoherenceRequestType:L1_DG) { - return GenericRequestType:DOWNGRADE; - } else if(type == CoherenceRequestType:WB_ACK) { - return GenericRequestType:WB_ACK; - } else if(type == CoherenceRequestType:EXE_ACK) { - return GenericRequestType:EXE_ACK; - } else { - DEBUG_EXPR(type); - error("invalid CoherenceRequestType"); - } -} -*/ diff --git a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb index 1476ce34b..c3c92bd9d 100644 --- a/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb +++ b/src/mem/ruby/config/TwoLevel_SplitL1UnifiedL2.rb @@ -57,7 +57,7 @@ end net_ports = Array.new iface_ports = Array.new -assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol #{protocol}"); +assert((protocol == "MESI_CMP_directory" or protocol == "MOESI_CMP_directory"), __FILE__+" cannot be used with protocol '#{protocol}'"); require protocol+".rb" diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc index bddc8781f..0edfedc43 100644 --- a/src/mem/slicc/symbols/StateMachine.cc +++ b/src/mem/slicc/symbols/StateMachine.cc @@ -791,101 +791,7 @@ void StateMachine::printCWakeup(ostream& out, string component) << component << "InPort " << port->toString() << endl; string output = port->lookupPair("c_code_in_port"); - string::size_type pos = output.find("TransitionResult result = doTransition((L1Cache_mandatory_request_type_to_event(((*in_msg_ptr)).m_Type)), L1Cache_getState(addr), addr);"); - assert(pos != string::npos); - string atomics_string = "\n \ - if ((((*in_msg_ptr)).m_Type) == CacheRequestType_ATOMIC) { \n \ - if (servicing_atomic == 0) { \n \ - if (locked_read_request1 == Address(-1)) { \n \ - assert(read_counter == 0); \n \ - locked_read_request1 = addr; \n \ - assert(read_counter == 0); \n \ - read_counter++; \n \ - } \n \ - else if (addr == locked_read_request1) { \n \ - ; // do nothing \n\ - } \n \ - else { \n \ - assert(0); // should never be here if servicing one request at a time \n\ - } \n \ - } \n \ - else if (!started_receiving_writes) { \n \ - if (servicing_atomic == 1) { \n \ - if (locked_read_request2 == Address(-1)) { \n \ - assert(locked_read_request1 != Address(-1)); \n \ - assert(read_counter == 1); \n \ - locked_read_request2 = addr; \n \ - assert(read_counter == 1); \n \ - read_counter++; \n \ - } \n \ - else if (addr == locked_read_request2) { \n \ - ; // do nothing \n\ - } \n \ - else { \n \ - assert(0); // should never be here if servicing one request at a time \n\ - } \n \ - } \n \ - else if (servicing_atomic == 2) { \n \ - if (locked_read_request3 == Address(-1)) { \n \ - assert(locked_read_request1 != Address(-1)); \n \ - assert(locked_read_request2 != Address(-1)); \n \ - assert(read_counter == 1); \n \ - locked_read_request3 = addr; \n \ - assert(read_counter == 2); \n \ - read_counter++; \n \ - } \n \ - else if (addr == locked_read_request3) { \n \ - ; // do nothing \n\ - } \n \ - else { \n \ - assert(0); // should never be here if servicing one request at a time \n\ - } \n \ - } \n \ - else if (servicing_atomic == 3) { \n \ - if (locked_read_request4 == Address(-1)) { \n \ - assert(locked_read_request1 != Address(-1)); \n \ - assert(locked_read_request2 != Address(-1)); \n \ - assert(locked_read_request3 != Address(-1)); \n \ - assert(read_counter == 1); \n \ - locked_read_request4 = addr; \n \ - assert(read_counter == 3); \n \ - read_counter++; \n \ - } \n \ - else if (addr == locked_read_request4) { \n \ - ; // do nothing \n\ - } \n \ - else { \n \ - assert(0); // should never be here if servicing one request at a time \n\ - } \n \ - } \n \ - else { \n \ - assert(0); \n \ - } \n \ - } \n \ - } \n \ - else { \n \ - if (servicing_atomic > 0) { \n \ - // reset \n \ - servicing_atomic = 0; \n \ - read_counter = 0; \n \ - started_receiving_writes = false; \n \ - locked_read_request1 = Address(-1); \n \ - locked_read_request2 = Address(-1); \n \ - locked_read_request3 = Address(-1); \n \ - locked_read_request4 = Address(-1); \n \ - } \n \ - } \n \ - "; - - // output.insert(pos, atomics_string); - /*string foo = "// Cannot do anything with this transition, go check next doable transition (mostly likely of next port)\n"; - string::size_type next_pos = output.find(foo, pos); - next_pos = next_pos + foo.length(); - - assert(next_pos != string::npos); - string complete = " }\n"; - output.insert(next_pos, complete);*/ - //out << port->lookupPair("c_code_in_port"); + out << output; out << endl; } |