6 files changed, 11 insertions, 13 deletions
diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 12657e177..b398af959 100644
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -47,7 +47,8 @@ class BaseBus(MemObject):
     abstract = True
     slave = VectorSlavePort("vector port for connecting masters")
     master = VectorMasterPort("vector port for connecting slaves")
-    clock = Param.Clock("1GHz", "bus clock speed")
+    # Override the default clock
+    clock = '1GHz'
     header_cycles = Param.Int(1, "cycles of overhead per transaction")
     width = Param.Int(8, "bus width (bytes)")
     block_size = Param.Int(64, "The default block size if not set by " \
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index e2e858494..0f33cc0bf 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -26,8 +26,8 @@
 #
 # Authors: Ron Dreslinski
 
-from m5.SimObject import SimObject
+from ClockedObject import ClockedObject
 
-class MemObject(SimObject):
+class MemObject(ClockedObject):
     type = 'MemObject'
     abstract = True
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index 583e60a15..829d694de 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -47,7 +47,6 @@
  * Definition of a bus object.
  */
 
-#include "base/intmath.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "debug/Bus.hh"
@@ -56,7 +55,7 @@
 #include "mem/bus.hh"
 
 BaseBus::BaseBus(const BaseBusParams *p)
-    : MemObject(p), clock(p->clock),
+    : MemObject(p),
       headerCycles(p->header_cycles), width(p->width),
       defaultPortID(InvalidPortID),
       useDefaultRange(p->use_default_range),
@@ -114,7 +113,7 @@ BaseBus::calcPacketTiming(PacketPtr pkt)
 {
     // determine the current time rounded to the closest following
     // clock edge
-    Tick now = divCeil(curTick(), clock) * clock;
+    Tick now = nextCycle();
 
     Tick headerTime = now + headerCycles * clock;
 
@@ -287,7 +286,7 @@ BaseBus::Layer<PortClass>::retryWaiting()
 
         // determine the current time rounded to the closest following
         // clock edge
-        Tick now = divCeil(curTick(), clock) * clock;
+        Tick now = bus.nextCycle();
 
         occupyLayer(now + clock);
     }
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index d4c3b4724..ac35581b1 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -228,8 +228,6 @@ class BaseBus : public MemObject
 
     };
 
-    /** the clock speed for the bus */
-    Tick clock;
     /** cycles of overhead per transaction */
     int headerCycles;
     /** the width of the bus in bytes */
diff --git a/src/mem/mem_object.cc b/src/mem/mem_object.cc
index ce8badbe7..cc05b7fc2 100644
--- a/src/mem/mem_object.cc
+++ b/src/mem/mem_object.cc
@@ -44,7 +44,7 @@
 #include "mem/mem_object.hh"
 
 MemObject::MemObject(const Params *params)
-    : SimObject(params)
+    : ClockedObject(params)
 {
 }
 
diff --git a/src/mem/mem_object.hh b/src/mem/mem_object.hh
index d8e6bdcb0..6cc0c4fd3 100644
--- a/src/mem/mem_object.hh
+++ b/src/mem/mem_object.hh
@@ -51,13 +51,13 @@
 
 #include "mem/port.hh"
 #include "params/MemObject.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
 
 /**
- * The MemObject class extends the SimObject with accessor functions
+ * The MemObject class extends the ClockedObject with accessor functions
  * to get its master and slave ports.
  */
-class MemObject : public SimObject
+class MemObject : public ClockedObject
 {
   public:
     typedef MemObjectParams Params;