7 files changed, 57 insertions, 8 deletions

diff --git a/src/mem/request.hh b/src/mem/request.hh
index f2cc4647c..8d1697ad2 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -194,6 +194,13 @@ class Request : public FastAlloc
         setPhys(paddr, size, flags, time);
     }
 
+    Request(Addr paddr, int size, Flags flags, Tick time, Addr pc)
+    {
+        setPhys(paddr, size, flags, time);
+        privateFlags.set(VALID_PC);
+        _pc = pc;
+    }
+
     Request(int asid, Addr vaddr, int size, Flags flags, Addr pc,
             int cid, ThreadID tid)
     {
diff --git a/src/mem/ruby/common/SubBlock.hh b/src/mem/ruby/common/SubBlock.hh
index 753666a17..8acdd9f4d 100644
--- a/src/mem/ruby/common/SubBlock.hh
+++ b/src/mem/ruby/common/SubBlock.hh
@@ -75,7 +75,7 @@ private:
 
   // Data Members (m_ prefix)
   Address m_address;
-  Vector<uint> m_data;
+  Vector<uint8_t> m_data;
 };
 
 // Output operator declaration
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index 692c9ea81..e4742dbab 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -30,6 +30,7 @@
 #include "mem/physical.hh"
 #include "mem/ruby/system/RubyPort.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
+#include "cpu/rubytest/RubyTester.hh"
 
 uint16_t RubyPort::m_num_ports = 0;
 
@@ -205,11 +206,18 @@ RubyPort::M5Port::recvTiming(PacketPtr pkt)
     // sending them to our assigned ruby port.
     //
     RubyRequestType type = RubyRequestType_NULL;
+
+    //
+    // If valid, copy the pc to the ruby request
+    //
     Addr pc = 0;
+    if (pkt->req->hasPC()) {
+        pc = pkt->req->getPC();
+    }
+
     if (pkt->isRead()) {
         if (pkt->req->isInstFetch()) {
             type = RubyRequestType_IFETCH;
-            pc = pkt->req->getPC();
         } else {
             type = RubyRequestType_LD; 
         }
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index e57f663c9..267b557ec 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -152,11 +152,10 @@ protected:
   MessageBuffer* m_mandatory_q_ptr;
     PioPort* pio_port;
 
-private:
-  static uint16_t m_num_ports;
-  uint16_t m_port_id;
-  uint64_t m_request_cnt;
-
+    //
+    // The pending request map is protected so that the Sequencer can access it.
+    // This is a temporary fix until the libruby inteface is cleaned
+    //
     struct RequestCookie {
         Packet *pkt;
         M5Port *m5Port;
@@ -167,6 +166,12 @@ private:
 
     typedef std::map<int64_t, RequestCookie*> RequestMap;
     static RequestMap pending_cpu_requests;
+
+private:
+  static uint16_t m_num_ports;
+  uint16_t m_port_id;
+  uint64_t m_request_cnt;
+
     static void ruby_hit_callback(int64_t req_id);
 
     M5Port* physMemPort;
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 00ae5364c..578dcbf58 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -41,6 +41,7 @@
 #include "mem/gems_common/Map.hh"
 #include "mem/ruby/buffers/MessageBuffer.hh"
 #include "mem/ruby/slicc_interface/AbstractController.hh"
+#include "cpu/rubytest/RubyTester.hh"
 
 #include "params/RubySequencer.hh"
 
@@ -74,7 +75,8 @@ Sequencer::Sequencer(const Params *p)
     m_dataCache_ptr = p->dcache;
     m_max_outstanding_requests = p->max_outstanding_requests;
     m_deadlock_threshold = p->deadlock_threshold;
-    
+    m_usingRubyTester = p->using_ruby_tester;
+
     assert(m_max_outstanding_requests > 0);
     assert(m_deadlock_threshold > 0);
     assert(m_instCache_ptr != NULL);
@@ -344,6 +346,30 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
     }
   }
 
+  //
+  // If using the RubyTester, update the RubyTester sender state's subBlock 
+  // with the recieved data.  The tester will later access this state.
+  // Note: RubyPort will access it's sender state before the RubyTester.
+  //
+  if (m_usingRubyTester) {
+      //
+      // Since the hit callback func only takes a request id, we must iterate
+      // through the requests and update the packet's subBlock here.
+      // All this would be fixed if we could attach a M5 pkt pointer to the
+      // ruby request, however that change will break the libruby interface so
+      // we'll hold off on that for now.
+      //
+      RequestMap::iterator i = pending_cpu_requests.find(srequest->id);
+      if (i == pending_cpu_requests.end())
+          panic("could not find pending request %d\n", srequest->id);
+      RequestCookie *cookie = i->second;
+      Packet *pkt = cookie->pkt;
+
+      RubyTester::SenderState* testerSenderState;
+      testerSenderState = safe_cast<RubyTester::SenderState*>(pkt->senderState);
+      testerSenderState->subBlock->mergeFrom(data);
+  }
+
   m_hit_callback(srequest->id);
   delete srequest;
 }
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index f24edbf74..a571092f7 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -129,6 +129,8 @@ private:
   int m_load_waiting_on_store_cycles;
   int m_load_waiting_on_load_cycles;
 
+  bool m_usingRubyTester;
+
   class SequencerWakeupEvent : public Event
   {
       Sequencer *m_sequencer_ptr;
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 30cb9add0..be8ac94b8 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -20,6 +20,7 @@ class RubySequencer(RubyPort):
         "max requests (incl. prefetches) outstanding")
     deadlock_threshold = Param.Int(500000,
         "max outstanding cycles for a request before deadlock/livelock declared")
+    using_ruby_tester = Param.Bool(False, "")
 
 class DMASequencer(RubyPort):
     type = 'DMASequencer'