summaryrefslogtreecommitdiff
path: root/src/mem
diff options
context:
space:
mode:
Diffstat (limited to 'src/mem')
-rw-r--r--src/mem/protocol/MI_example-dir.sm13
-rw-r--r--src/mem/protocol/MI_example-dma.sm10
-rw-r--r--src/mem/protocol/MI_example-msg.sm2
-rw-r--r--src/mem/ruby/common/DataBlock.hh4
-rw-r--r--src/mem/ruby/config/MI_example-homogeneous.rb4
-rw-r--r--src/mem/ruby/system/DMASequencer.cc37
-rw-r--r--src/mem/ruby/system/DMASequencer.hh1
-rw-r--r--src/mem/slicc/symbols/StateMachine.cc17
8 files changed, 52 insertions, 36 deletions
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index a275e4b8d..fa8903d47 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -129,9 +129,9 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D
if (dmaRequestQueue_in.isReady()) {
peek(dmaRequestQueue_in, DMARequestMsg) {
if (in_msg.Type == DMARequestType:READ) {
- trigger(Event:DMA_READ, in_msg.PhysicalAddress);
+ trigger(Event:DMA_READ, in_msg.LineAddress);
} else if (in_msg.Type == DMARequestType:WRITE) {
- trigger(Event:DMA_WRITE, in_msg.PhysicalAddress);
+ trigger(Event:DMA_WRITE, in_msg.LineAddress);
} else {
error("Invalid message");
}
@@ -267,6 +267,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D
peek(memQueue_in, MemoryMsg) {
enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
out_msg.PhysicalAddress := address;
+ out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(map_Address_to_DMA(address));
@@ -281,6 +282,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D
peek(requestQueue_in, RequestMsg) {
enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
out_msg.PhysicalAddress := address;
+ out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:DATA;
out_msg.DataBlk := in_msg.DataBlk; // we send the entire data block and rely on the dma controller to split it up if need be
out_msg.Destination.add(map_Address_to_DMA(address));
@@ -292,6 +294,7 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D
action(da_sendDMAAck, "da", desc="Send Ack to DMA controller") {
enqueue(dmaResponseNetwork_out, DMAResponseMsg, latency="MEMORY_LATENCY") {
out_msg.PhysicalAddress := address;
+ out_msg.LineAddress := address;
out_msg.Type := DMAResponseType:ACK;
out_msg.Destination.add(map_Address_to_DMA(address));
out_msg.MessageSize := MessageSizeType:Writeback_Control;
@@ -355,12 +358,6 @@ machine(Directory, "Directory protocol") : LATENCY_TO_MEM_CTRL_LATENCY LATENCY_D
}
}
- action(dw_writeDMAData, "dw", desc="DMA Write data to memory") {
- peek(dmaRequestQueue_in, DMARequestMsg) {
- directory[in_msg.PhysicalAddress].DataBlk.copyPartial(in_msg.DataBlk, in_msg.Offset, in_msg.Len);
- }
- }
-
action(dwt_writeDMADataFromTBE, "dwt", desc="DMA Write data to memory from TBE") {
directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, TBEs[address].Offset, TBEs[address].Len);
}
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index 1f929cf9b..d5de18552 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -39,9 +39,9 @@ machine(DMA, "DMA Controller") {
if (dmaRequestQueue_in.isReady()) {
peek(dmaRequestQueue_in, DMARequestMsg) {
if (in_msg.Type == DMARequestType:READ ) {
- trigger(Event:ReadRequest, in_msg.PhysicalAddress);
+ trigger(Event:ReadRequest, in_msg.LineAddress);
} else if (in_msg.Type == DMARequestType:WRITE) {
- trigger(Event:WriteRequest, in_msg.PhysicalAddress);
+ trigger(Event:WriteRequest, in_msg.LineAddress);
} else {
error("Invalid request type");
}
@@ -53,9 +53,9 @@ machine(DMA, "DMA Controller") {
if (dmaResponseQueue_in.isReady()) {
peek( dmaResponseQueue_in, DMAResponseMsg) {
if (in_msg.Type == DMAResponseType:ACK) {
- trigger(Event:Ack, in_msg.PhysicalAddress);
+ trigger(Event:Ack, in_msg.LineAddress);
} else if (in_msg.Type == DMAResponseType:DATA) {
- trigger(Event:Data, in_msg.PhysicalAddress);
+ trigger(Event:Data, in_msg.LineAddress);
} else {
error("Invalid response type");
}
@@ -67,6 +67,7 @@ machine(DMA, "DMA Controller") {
peek(dmaRequestQueue_in, DMARequestMsg) {
enqueue(reqToDirectory_out, DMARequestMsg) {
out_msg.PhysicalAddress := address;
+ out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:READ;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
@@ -80,6 +81,7 @@ machine(DMA, "DMA Controller") {
peek(dmaRequestQueue_in, DMARequestMsg) {
enqueue(reqToDirectory_out, DMARequestMsg) {
out_msg.PhysicalAddress := address;
+ out_msg.LineAddress := in_msg.LineAddress;
out_msg.Type := DMARequestType:WRITE;
out_msg.DataBlk := in_msg.DataBlk;
out_msg.Len := in_msg.Len;
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm
index 56c2e2e01..8c0afed2e 100644
--- a/src/mem/protocol/MI_example-msg.sm
+++ b/src/mem/protocol/MI_example-msg.sm
@@ -104,6 +104,7 @@ enumeration(DMAResponseType, desc="...", default="DMAResponseType_NULL") {
structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
DMARequestType Type, desc="Request type (read/write)";
Address PhysicalAddress, desc="Physical address for this request";
+ Address LineAddress, desc="Line address for this request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
int Offset, desc="The offset into the datablock";
@@ -114,6 +115,7 @@ structure(DMARequestMsg, desc="...", interface="NetworkMessage") {
structure(DMAResponseMsg, desc="...", interface="NetworkMessage") {
DMAResponseType Type, desc="Response type (DATA/ACK)";
Address PhysicalAddress, desc="Physical address for this request";
+ Address LineAddress, desc="Line address for this request";
NetDest Destination, desc="Destination";
DataBlock DataBlk, desc="DataBlk attached to this request";
MessageSizeType MessageSize, desc="size category of the message";
diff --git a/src/mem/ruby/common/DataBlock.hh b/src/mem/ruby/common/DataBlock.hh
index 2a0811f76..ccd73c36b 100644
--- a/src/mem/ruby/common/DataBlock.hh
+++ b/src/mem/ruby/common/DataBlock.hh
@@ -108,8 +108,8 @@ void DataBlock::print(ostream& out) const
{
int size = RubySystem::getBlockSizeBytes();
out << "[ ";
- for (int i = 0; i < size; i+=4) {
- out << hex << *((uint32*)(&(m_data[i]))) << " ";
+ for (int i = 0; i < size; i++) {
+ out << setw(2) << setfill('0') << hex << "0x" << (int)m_data[i] << " ";
}
out << dec << "]" << flush;
}
diff --git a/src/mem/ruby/config/MI_example-homogeneous.rb b/src/mem/ruby/config/MI_example-homogeneous.rb
index 7dffb3957..d43e384e5 100644
--- a/src/mem/ruby/config/MI_example-homogeneous.rb
+++ b/src/mem/ruby/config/MI_example-homogeneous.rb
@@ -10,10 +10,10 @@ require "cfg.rb"
# default values
-num_cores = 16
+num_cores = 2
L1_CACHE_SIZE_KB = 32
L1_CACHE_ASSOC = 8
-L1_CACHE_LATENCY = 2
+L1_CACHE_LATENCY = 1
num_memories = 2
memory_size_mb = 1024
NUM_DMA = 1
diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc
index 8f7b1c912..58ec7bb45 100644
--- a/src/mem/ruby/system/DMASequencer.cc
+++ b/src/mem/ruby/system/DMASequencer.cc
@@ -29,6 +29,7 @@ void DMASequencer::init(const vector<string> & argv)
m_mandatory_q_ptr = m_controller->getMandatoryQueue();
m_is_busy = false;
+ m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits());
}
int64_t DMASequencer::makeRequest(const RubyRequest & request)
@@ -53,7 +54,7 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request)
assert(0);
}
- assert(!m_is_busy);
+ assert(!m_is_busy); // only support one outstanding DMA request
m_is_busy = true;
active_request.start_paddr = paddr;
@@ -66,14 +67,15 @@ int64_t DMASequencer::makeRequest(const RubyRequest & request)
DMARequestMsg msg;
msg.getPhysicalAddress() = Address(paddr);
+ msg.getLineAddress() = line_address(msg.getPhysicalAddress());
msg.getType() = write ? DMARequestType_WRITE : DMARequestType_READ;
- msg.getOffset() = paddr & RubyConfig::dataBlockMask();
- msg.getLen() = (msg.getOffset() + len) < RubySystem::getBlockSizeBytes() ?
- (msg.getOffset() + len) :
+ msg.getOffset() = paddr & m_data_block_mask;
+ msg.getLen() = (msg.getOffset() + len) <= RubySystem::getBlockSizeBytes() ?
+ len :
RubySystem::getBlockSizeBytes() - msg.getOffset();
if (write) {
msg.getType() = DMARequestType_WRITE;
- msg.getDataBlk().setData(data, 0, msg.getLen());
+ msg.getDataBlk().setData(data, msg.getOffset(), msg.getLen());
} else {
msg.getType() = DMARequestType_READ;
}
@@ -94,15 +96,20 @@ void DMASequencer::issueNext()
}
DMARequestMsg msg;
- msg.getPhysicalAddress() = Address(active_request.start_paddr + active_request.bytes_completed);
- assert((msg.getPhysicalAddress().getAddress() & RubyConfig::dataBlockMask()) == 0);
+ msg.getPhysicalAddress() = Address(active_request.start_paddr +
+ active_request.bytes_completed);
+ assert((msg.getPhysicalAddress().getAddress() & m_data_block_mask) == 0);
+ msg.getLineAddress() = line_address(msg.getPhysicalAddress());
msg.getOffset() = 0;
- msg.getType() = active_request.write ? DMARequestType_WRITE : DMARequestType_READ;
- msg.getLen() = active_request.len - active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
- active_request.len - active_request.bytes_completed :
- RubySystem::getBlockSizeBytes();
+ msg.getType() = (active_request.write ? DMARequestType_WRITE :
+ DMARequestType_READ);
+ msg.getLen() = (active_request.len -
+ active_request.bytes_completed < RubySystem::getBlockSizeBytes() ?
+ active_request.len - active_request.bytes_completed :
+ RubySystem::getBlockSizeBytes());
if (active_request.write) {
- msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed], 0, msg.getLen());
+ msg.getDataBlk().setData(&active_request.data[active_request.bytes_completed],
+ 0, msg.getLen());
msg.getType() = DMARequestType_WRITE;
} else {
msg.getType() = DMARequestType_READ;
@@ -117,8 +124,10 @@ void DMASequencer::dataCallback(const DataBlock & dblk)
int len = active_request.bytes_issued - active_request.bytes_completed;
int offset = 0;
if (active_request.bytes_completed == 0)
- offset = active_request.start_paddr & RubyConfig::dataBlockMask();
- memcpy(&active_request.data[active_request.bytes_completed], dblk.getData(offset, len), len);
+ offset = active_request.start_paddr & m_data_block_mask;
+ assert( active_request.write == false );
+ memcpy(&active_request.data[active_request.bytes_completed],
+ dblk.getData(offset, len), len);
issueNext();
}
diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh
index 2665549e3..1f60b95ec 100644
--- a/src/mem/ruby/system/DMASequencer.hh
+++ b/src/mem/ruby/system/DMASequencer.hh
@@ -41,6 +41,7 @@ private:
int m_version;
AbstractController* m_controller;
bool m_is_busy;
+ uint64_t m_data_block_mask;
DMARequest active_request;
int num_active_requests;
MessageBuffer* m_mandatory_q_ptr;
diff --git a/src/mem/slicc/symbols/StateMachine.cc b/src/mem/slicc/symbols/StateMachine.cc
index 64c7ae24a..b2ec4d676 100644
--- a/src/mem/slicc/symbols/StateMachine.cc
+++ b/src/mem/slicc/symbols/StateMachine.cc
@@ -314,7 +314,7 @@ void StateMachine::printControllerH(ostream& out, string component)
out << " NodeID m_version;" << endl;
out << " Network* m_net_ptr;" << endl;
out << " MachineID m_machineID;" << endl;
- out << " static " << component << "_Profiler s_profiler;" << endl;
+ out << " " << component << "_Profiler s_profiler;" << endl;
out << " static int m_num_controllers;" << endl;
// internal function protypes
@@ -392,10 +392,6 @@ void StateMachine::printControllerC(ostream& out, string component)
out << "stringstream " << component << "_" << "transitionComment;" << endl;
out << "#define APPEND_TRANSITION_COMMENT(str) (" << component << "_" << "transitionComment << str)" << endl;
- out << "/** \\brief static profiler defn */" << endl;
- out << component << "_Profiler " << component << "_Controller::s_profiler;" << endl;
- out << endl;
-
out << "/** \\brief constructor */" << endl;
out << component << "_Controller::" << component
// << "_Controller(int version, Network* net_ptr)" << endl;
@@ -478,6 +474,7 @@ void StateMachine::printControllerC(ostream& out, string component)
// initialize objects
out << " // Objects" << endl;
+ out << " s_profiler.setVersion(m_version);" << endl;
for(int i=0; i < numObjects(); i++) {
const Var* var = m_objs[i];
if (!var->existPair("network")) {
@@ -1116,6 +1113,7 @@ void StateMachine::printProfilerH(ostream& out, string component)
out << "class " << component << "_Profiler {" << endl;
out << "public:" << endl;
out << " " << component << "_Profiler();" << endl;
+ out << " void setVersion(int version);" << endl;
out << " void countTransition(" << component << "_State state, " << component << "_Event event);" << endl;
out << " void possibleTransition(" << component << "_State state, " << component << "_Event event);" << endl;
out << " void dumpStats(ostream& out) const;" << endl;
@@ -1124,6 +1122,7 @@ void StateMachine::printProfilerH(ostream& out, string component)
out << " int m_counters[" << component << "_State_NUM][" << component << "_Event_NUM];" << endl;
out << " int m_event_counters[" << component << "_Event_NUM];" << endl;
out << " bool m_possible[" << component << "_State_NUM][" << component << "_Event_NUM];" << endl;
+ out << " int m_version;" << endl;
out << "};" << endl;
out << "#endif // " << component << "_PROFILER_H" << endl;
}
@@ -1150,6 +1149,12 @@ void StateMachine::printProfilerC(ostream& out, string component)
out << " }" << endl;
out << "}" << endl;
+ // setVersion
+ out << "void " << component << "_Profiler::setVersion(int version)" << endl;
+ out << "{" << endl;
+ out << " m_version = version;" << endl;
+ out << "}" << endl;
+
// Clearstats
out << "void " << component << "_Profiler::clearStats()" << endl;
out << "{" << endl;
@@ -1180,7 +1185,7 @@ void StateMachine::printProfilerC(ostream& out, string component)
// dumpStats
out << "void " << component << "_Profiler::dumpStats(ostream& out) const" << endl;
out << "{" << endl;
- out << " out << \" --- " << component << " ---\" << endl;" << endl;
+ out << " out << \" --- " << component << " \" << m_version << \" ---\" << endl;" << endl;
out << " out << \" - Event Counts -\" << endl;" << endl;
out << " for (int event = 0; event < " << component << "_Event_NUM; event++) {" << endl;
out << " int count = m_event_counters[event];" << endl;
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-19 09:42:19 +0000