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-rw-r--r--src/mem/bus.cc10
-rw-r--r--src/mem/bus.hh8
-rw-r--r--src/mem/cache/base.cc4
-rw-r--r--src/mem/cache/base.hh7
-rw-r--r--src/mem/cache/blk.hh4
-rw-r--r--src/mem/cache/mshr.hh2
-rw-r--r--src/mem/cache/prefetch/base.hh2
-rw-r--r--src/mem/cache/tags/fa_lru.cc16
-rw-r--r--src/mem/cache/tags/fa_lru.hh19
-rw-r--r--src/mem/cache/tags/iic.cc20
-rw-r--r--src/mem/cache/tags/iic.hh51
-rw-r--r--src/mem/cache/tags/lru.cc19
-rw-r--r--src/mem/cache/tags/lru.hh18
-rw-r--r--src/mem/gems_common/ioutil/confio.cc4
-rw-r--r--src/mem/packet.hh4
-rw-r--r--src/mem/page_table.cc2
-rw-r--r--src/mem/physical.cc18
-rw-r--r--src/mem/physical.hh4
-rw-r--r--src/mem/port.cc5
-rw-r--r--src/mem/port.hh4
-rw-r--r--src/mem/rubymem.cc2
21 files changed, 116 insertions, 107 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index b9cdff242..001c37a24 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -593,27 +593,27 @@ Bus::addressRanges(AddrRangeList &resp, bool &snoop, int id)
}
}
-int
+unsigned
Bus::findBlockSize(int id)
{
if (cachedBlockSizeValid)
return cachedBlockSize;
- int max_bs = -1;
+ unsigned max_bs = 0;
PortIter p_end = portMap.end();
for (PortIter p_iter = portMap.begin(); p_iter != p_end; p_iter++) {
- int tmp_bs = interfaces[p_iter->second]->peerBlockSize();
+ unsigned tmp_bs = interfaces[p_iter->second]->peerBlockSize();
if (tmp_bs > max_bs)
max_bs = tmp_bs;
}
SnoopIter s_end = snoopPorts.end();
for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
- int tmp_bs = (*s_iter)->peerBlockSize();
+ unsigned tmp_bs = (*s_iter)->peerBlockSize();
if (tmp_bs > max_bs)
max_bs = tmp_bs;
}
- if (max_bs <= 0)
+ if (max_bs == 0)
max_bs = defaultBlockSize;
if (max_bs != 64)
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 4de42b538..97a65c8a9 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -119,7 +119,7 @@ class Bus : public MemObject
// Ask the bus to ask everyone on the bus what their block size is and
// take the max of it. This might need to be changed a bit if we ever
// support multiple block sizes.
- virtual int deviceBlockSize()
+ virtual unsigned deviceBlockSize() const
{ return bus->findBlockSize(id); }
};
@@ -259,7 +259,7 @@ class Bus : public MemObject
* @param id id of the busport that made the request
* @return the max of all the sizes
*/
- int findBlockSize(int id);
+ unsigned findBlockSize(int id);
BusFreeEvent busIdle;
@@ -308,8 +308,8 @@ class Bus : public MemObject
/** Has the user specified their own default responder? */
bool responderSet;
- int defaultBlockSize;
- int cachedBlockSize;
+ unsigned defaultBlockSize;
+ unsigned cachedBlockSize;
bool cachedBlockSizeValid;
// Cache for the peer port interfaces
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 29fa97544..fe1f580bd 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -85,8 +85,8 @@ BaseCache::CachePort::checkFunctional(PacketPtr pkt)
}
-int
-BaseCache::CachePort::deviceBlockSize()
+unsigned
+BaseCache::CachePort::deviceBlockSize() const
{
return cache->getBlockSize();
}
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index b77427c90..24f993383 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -104,7 +104,7 @@ class BaseCache : public MemObject
virtual void recvStatusChange(Status status);
- virtual int deviceBlockSize();
+ virtual unsigned deviceBlockSize() const;
bool recvRetryCommon();
@@ -180,7 +180,7 @@ class BaseCache : public MemObject
}
/** Block size of this cache */
- const int blkSize;
+ const unsigned blkSize;
/**
* The latency of a hit in this device.
@@ -372,7 +372,8 @@ class BaseCache : public MemObject
* Query block size of a cache.
* @return The block size
*/
- int getBlockSize() const
+ unsigned
+ getBlockSize() const
{
return blkSize;
}
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index ab15355bd..369de6d11 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -157,7 +157,7 @@ class CacheBlk
*/
bool isWritable() const
{
- const int needed_bits = BlkWritable | BlkValid;
+ const State needed_bits = BlkWritable | BlkValid;
return (status & needed_bits) == needed_bits;
}
@@ -169,7 +169,7 @@ class CacheBlk
*/
bool isReadable() const
{
- const int needed_bits = BlkReadable | BlkValid;
+ const State needed_bits = BlkReadable | BlkValid;
return (status & needed_bits) == needed_bits;
}
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index 13395d314..26eef2cac 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -140,7 +140,7 @@ class MSHR : public Packet::SenderState, public Printable
/** Thread number of the miss. */
ThreadID threadNum;
/** The number of currently allocated targets. */
- short ntargets;
+ unsigned short ntargets;
/** Data buffer (if needed). Currently used only for pending
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index fc027cb3b..b5f33a455 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -54,7 +54,7 @@ class BasePrefetcher
// PARAMETERS
/** The number of MSHRs in the Prefetch Queue. */
- const int size;
+ const unsigned size;
/** Pointr to the parent cache. */
BaseCache* cache;
diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index 0e0121f67..122e6e14b 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -42,7 +42,7 @@
using namespace std;
-FALRU::FALRU(int _blkSize, int _size, int hit_latency)
+FALRU::FALRU(unsigned _blkSize, unsigned _size, unsigned hit_latency)
: blkSize(_blkSize), size(_size),
numBlks(size/blkSize), hitLatency(hit_latency)
{
@@ -78,10 +78,10 @@ FALRU::FALRU(int _blkSize, int _size, int hit_latency)
tail->next = NULL;
tail->inCache = 0;
- int index = (1 << 17) / blkSize;
- int j = 0;
+ unsigned index = (1 << 17) / blkSize;
+ unsigned j = 0;
int flags = cacheMask;
- for (int i = 1; i < numBlks-1; i++) {
+ for (unsigned i = 1; i < numBlks - 1; i++) {
blks[i].inCache = flags;
if (i == index - 1){
cacheBoundaries[j] = &(blks[i]);
@@ -118,7 +118,7 @@ FALRU::regStats(const string &name)
.desc("The number of accesses to the FA LRU cache.")
;
- for (int i = 0; i < numCaches+1; ++i) {
+ for (unsigned i = 0; i <= numCaches; ++i) {
stringstream size_str;
if (i < 3){
size_str << (1<<(i+7)) <<"K";
@@ -164,7 +164,7 @@ FALRU::accessBlock(Addr addr, int &lat, int *inCache)
if (blk && blk->isValid()) {
assert(blk->tag == blkAddr);
tmp_in_cache = blk->inCache;
- for (int i = 0; i < numCaches; i++) {
+ for (unsigned i = 0; i < numCaches; i++) {
if (1<<i & blk->inCache) {
hits[i]++;
} else {
@@ -177,7 +177,7 @@ FALRU::accessBlock(Addr addr, int &lat, int *inCache)
}
} else {
blk = NULL;
- for (int i = 0; i < numCaches+1; ++i) {
+ for (unsigned i = 0; i <= numCaches; ++i) {
misses[i]++;
}
}
@@ -236,7 +236,7 @@ void
FALRU::moveToHead(FALRUBlk *blk)
{
int updateMask = blk->inCache ^ cacheMask;
- for (int i = 0; i < numCaches; i++){
+ for (unsigned i = 0; i < numCaches; i++){
if ((1<<i) & updateMask) {
cacheBoundaries[i]->inCache &= ~(1<<i);
cacheBoundaries[i] = cacheBoundaries[i]->prev;
diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 23d09d709..4e6bccc1d 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -78,22 +78,23 @@ class FALRU : public BaseTags
typedef FALRUBlk BlkType;
/** Typedef a list of pointers to the local block type. */
typedef std::list<FALRUBlk*> BlkList;
+
protected:
/** The block size of the cache. */
- const int blkSize;
+ const unsigned blkSize;
/** The size of the cache. */
- const int size;
+ const unsigned size;
/** The number of blocks in the cache. */
- const int numBlks; // calculated internally
+ const unsigned numBlks; // calculated internally
/** The hit latency of the cache. */
- const int hitLatency;
+ const unsigned hitLatency;
/** Array of pointers to blocks at the cache size boundaries. */
FALRUBlk **cacheBoundaries;
/** A mask for the FALRUBlk::inCache bits. */
int cacheMask;
/** The number of different size caches being tracked. */
- int numCaches;
+ unsigned numCaches;
/** The cache blocks. */
FALRUBlk *blks;
@@ -156,7 +157,7 @@ public:
* @param size The size of the cache.
* @param hit_latency The hit latency of the cache.
*/
- FALRU(int blkSize, int size, int hit_latency);
+ FALRU(unsigned blkSize, unsigned size, unsigned hit_latency);
/**
* Register the stats for this object.
@@ -214,7 +215,8 @@ public:
* Return the block size of this cache.
* @return The block size.
*/
- int getBlockSize()
+ unsigned
+ getBlockSize() const
{
return blkSize;
}
@@ -223,7 +225,8 @@ public:
* Return the subblock size of this cache, always the block size.
* @return The block size.
*/
- int getSubBlockSize()
+ unsigned
+ getSubBlockSize() const
{
return blkSize;
}
diff --git a/src/mem/cache/tags/iic.cc b/src/mem/cache/tags/iic.cc
index 7bc2543c5..b9ba5256b 100644
--- a/src/mem/cache/tags/iic.cc
+++ b/src/mem/cache/tags/iic.cc
@@ -66,8 +66,6 @@ IIC::IIC(IIC::Params &params) :
tagNull(numTags),
primaryBound(hashSets * assoc)
{
- int i;
-
// Check parameters
if (blkSize < 4 || !isPowerOf2(blkSize)) {
fatal("Block size must be at least 4 and a power of 2");
@@ -104,10 +102,10 @@ IIC::IIC(IIC::Params &params) :
// Allocate storage for both internal data and block fast access data.
// We allocate it as one large chunk to reduce overhead and to make
// deletion easier.
- int data_index = 0;
+ unsigned data_index = 0;
dataStore = new uint8_t[(numBlocks + numTags) * blkSize];
dataBlks = new uint8_t*[numBlocks];
- for (i = 0; i < numBlocks; ++i) {
+ for (unsigned i = 0; i < numBlocks; ++i) {
dataBlks[i] = &dataStore[data_index];
freeDataBlock(i);
data_index += subSize;
@@ -118,15 +116,15 @@ IIC::IIC(IIC::Params &params) :
// allocate and init tag store
tagStore = new IICTag[numTags];
- int blkIndex = 0;
+ unsigned blkIndex = 0;
// allocate and init sets
sets = new IICSet[hashSets];
- for (i = 0; i < hashSets; ++i) {
+ for (unsigned i = 0; i < hashSets; ++i) {
sets[i].assoc = assoc;
sets[i].tags = new IICTag*[assoc];
sets[i].chain_ptr = tagNull;
- for (int j = 0; j < assoc; ++j) {
+ for (unsigned j = 0; j < assoc; ++j) {
IICTag *tag = &tagStore[blkIndex++];
tag->chain_ptr = tagNull;
tag->data_ptr.resize(numSub);
@@ -142,7 +140,7 @@ IIC::IIC(IIC::Params &params) :
assert(blkIndex == primaryBound);
- for (i = primaryBound; i < tagNull; i++) {
+ for (unsigned i = primaryBound; i < tagNull; i++) {
tagStore[i].chain_ptr = i+1;
//setup data ptrs to subblocks
tagStore[i].data_ptr.resize(numSub);
@@ -305,7 +303,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks)
unsigned long *tmp_data = new unsigned long[numSub];
// Get a enough subblocks for a full cache line
- for (int i = 0; i < numSub; ++i){
+ for (unsigned i = 0; i < numSub; ++i){
tmp_data[i] = getFreeDataBlock(writebacks);
assert(dataReferenceCount[tmp_data[i]]==0);
}
@@ -313,7 +311,7 @@ IIC::findVictim(Addr addr, PacketList &writebacks)
tag_ptr = getFreeTag(set, writebacks);
tag_ptr->set = set;
- for (int i=0; i< numSub; ++i) {
+ for (unsigned i = 0; i < numSub; ++i) {
tag_ptr->data_ptr[i] = tmp_data[i];
dataReferenceCount[tag_ptr->data_ptr[i]]++;
}
@@ -636,7 +634,7 @@ IIC::invalidateBlk(IIC::BlkType *tag_ptr)
void
IIC::cleanupRefs()
{
- for (int i = 0; i < numTags; ++i) {
+ for (unsigned i = 0; i < numTags; ++i) {
if (tagStore[i].isValid()) {
totalRefs += tagStore[i].refCount;
++sampledRefs;
diff --git a/src/mem/cache/tags/iic.hh b/src/mem/cache/tags/iic.hh
index 45c8ee801..994f7b8f7 100644
--- a/src/mem/cache/tags/iic.hh
+++ b/src/mem/cache/tags/iic.hh
@@ -167,46 +167,47 @@ class IIC : public BaseTags
typedef IICTag BlkType;
/** Typedef for list of pointers to the local block type. */
typedef std::list<IICTag*> BlkList;
+
protected:
/** The number of set in the primary table. */
- const int hashSets;
+ const unsigned hashSets;
/** The block size in bytes. */
- const int blkSize;
+ const unsigned blkSize;
/** The associativity of the primary table. */
- const int assoc;
+ const unsigned assoc;
/** The base hit latency. */
- const int hitLatency;
+ const unsigned hitLatency;
/** The subblock size, used for compression. */
- const int subSize;
+ const unsigned subSize;
/** The number of subblocks */
- const int numSub;
+ const unsigned numSub;
/** The number of bytes used by data pointers */
- const int trivialSize;
+ const unsigned trivialSize;
/** The amount to shift address to get the tag. */
- const int tagShift;
+ const unsigned tagShift;
/** The mask to get block offset bits. */
const unsigned blkMask;
/** The amount to shift to get the subblock number. */
- const int subShift;
+ const unsigned subShift;
/** The mask to get the correct subblock number. */
const unsigned subMask;
/** The latency of a hash lookup. */
- const int hashDelay;
+ const unsigned hashDelay;
/** The number of data blocks. */
- const int numBlocks;
+ const unsigned numBlocks;
/** The total number of tags in primary and secondary. */
- const int numTags;
+ const unsigned numTags;
/** The number of tags in the secondary tag store. */
- const int numSecondary;
+ const unsigned numSecondary;
/** The Null tag pointer. */
- const int tagNull;
+ const unsigned tagNull;
/** The last tag in the primary table. */
- const int primaryBound;
+ const unsigned primaryBound;
/** All of the tags */
IICTag *tagStore;
@@ -271,21 +272,21 @@ class IIC : public BaseTags
class Params {
public:
/** The size in bytes of the cache. */
- int size;
+ unsigned size;
/** The number of sets in the primary table. */
- int numSets;
+ unsigned numSets;
/** The block size in bytes. */
- int blkSize;
+ unsigned blkSize;
/** The associativity of the primary table. */
- int assoc;
+ unsigned assoc;
/** The number of cycles for each hash lookup. */
- int hashDelay;
+ unsigned hashDelay;
/** The number of cycles to read the data. */
- int hitLatency;
+ unsigned hitLatency;
/** The replacement policy. */
Repl *rp;
/** The subblock size in bytes. */
- int subblockSize;
+ unsigned subblockSize;
};
/**
@@ -322,7 +323,8 @@ class IIC : public BaseTags
* Return the block size.
* @return The block size.
*/
- int getBlockSize()
+ unsigned
+ getBlockSize() const
{
return blkSize;
}
@@ -331,7 +333,8 @@ class IIC : public BaseTags
* Return the subblock size.
* @return The subblock size.
*/
- int getSubBlockSize()
+ unsigned
+ getSubBlockSize() const
{
return subSize;
}
diff --git a/src/mem/cache/tags/lru.cc b/src/mem/cache/tags/lru.cc
index ff353ff6a..9371f193a 100644
--- a/src/mem/cache/tags/lru.cc
+++ b/src/mem/cache/tags/lru.cc
@@ -80,8 +80,10 @@ CacheSet::moveToHead(LRUBlk *blk)
// create and initialize a LRU/MRU cache structure
-LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) :
- numSets(_numSets), blkSize(_blkSize), assoc(_assoc), hitLatency(_hit_latency)
+LRU::LRU(unsigned _numSets, unsigned _blkSize, unsigned _assoc,
+ unsigned _hit_latency)
+ : numSets(_numSets), blkSize(_blkSize), assoc(_assoc),
+ hitLatency(_hit_latency)
{
// Check parameters
if (blkSize < 4 || !isPowerOf2(blkSize)) {
@@ -97,9 +99,6 @@ LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) :
fatal("access latency must be greater than zero");
}
- LRUBlk *blk;
- int i, j, blkIndex;
-
blkMask = blkSize - 1;
setShift = floorLog2(blkSize);
setMask = numSets - 1;
@@ -113,16 +112,16 @@ LRU::LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency) :
// allocate data storage in one big chunk
dataBlks = new uint8_t[numSets*assoc*blkSize];
- blkIndex = 0; // index into blks array
- for (i = 0; i < numSets; ++i) {
+ unsigned blkIndex = 0; // index into blks array
+ for (unsigned i = 0; i < numSets; ++i) {
sets[i].assoc = assoc;
sets[i].blks = new LRUBlk*[assoc];
// link in the data blocks
- for (j = 0; j < assoc; ++j) {
+ for (unsigned j = 0; j < assoc; ++j) {
// locate next cache block
- blk = &blks[blkIndex];
+ LRUBlk *blk = &blks[blkIndex];
blk->data = &dataBlks[blkSize*blkIndex];
++blkIndex;
@@ -233,7 +232,7 @@ LRU::invalidateBlk(LRU::BlkType *blk)
void
LRU::cleanupRefs()
{
- for (int i = 0; i < numSets*assoc; ++i) {
+ for (unsigned i = 0; i < numSets*assoc; ++i) {
if (blks[i].isValid()) {
totalRefs += blks[i].refCount;
++sampledRefs;
diff --git a/src/mem/cache/tags/lru.hh b/src/mem/cache/tags/lru.hh
index 466095ec9..2874d8f1f 100644
--- a/src/mem/cache/tags/lru.hh
+++ b/src/mem/cache/tags/lru.hh
@@ -92,15 +92,16 @@ class LRU : public BaseTags
typedef LRUBlk BlkType;
/** Typedef for a list of pointers to the local block class. */
typedef std::list<LRUBlk*> BlkList;
+
protected:
/** The number of sets in the cache. */
- const int numSets;
+ const unsigned numSets;
/** The number of bytes in a block. */
- const int blkSize;
+ const unsigned blkSize;
/** The associativity of the cache. */
- const int assoc;
+ const unsigned assoc;
/** The hit latency. */
- const int hitLatency;
+ const unsigned hitLatency;
/** The cache sets. */
CacheSet *sets;
@@ -127,7 +128,8 @@ public:
* @param _assoc The associativity of the cache.
* @param _hit_latency The latency in cycles for a hit.
*/
- LRU(int _numSets, int _blkSize, int _assoc, int _hit_latency);
+ LRU(unsigned _numSets, unsigned _blkSize, unsigned _assoc,
+ unsigned _hit_latency);
/**
* Destructor
@@ -138,7 +140,8 @@ public:
* Return the block size.
* @return the block size.
*/
- int getBlockSize()
+ unsigned
+ getBlockSize() const
{
return blkSize;
}
@@ -148,7 +151,8 @@ public:
* size.
* @return The block size.
*/
- int getSubBlockSize()
+ unsigned
+ getSubBlockSize() const
{
return blkSize;
}
diff --git a/src/mem/gems_common/ioutil/confio.cc b/src/mem/gems_common/ioutil/confio.cc
index db2bf0a35..a701473a7 100644
--- a/src/mem/gems_common/ioutil/confio.cc
+++ b/src/mem/gems_common/ioutil/confio.cc
@@ -156,7 +156,7 @@ void fprintAttr( FILE *fp, attr_value_t attr )
case Sim_Val_List:
fprintf(fp, "(");
- for (uint32 i = 0; i < attr.u.list.size; i++) {
+ for (int i = 0; i < attr.u.list.size; i++) {
fprintAttr(fp, attr.u.list.vector[i]);
if (i != attr.u.list.size -1) {
fprintf(fp, ", ");
@@ -188,7 +188,7 @@ void freeAttribute( attr_value_t *attr )
break;
case Sim_Val_List:
- for (uint32 i = 0; i < attr->u.list.size; i++) {
+ for (int i = 0; i < attr->u.list.size; i++) {
freeAttribute( &(attr->u.list.vector[i]) );
}
free( attr->u.list.vector );
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 672b00e3c..07c086cd5 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -257,7 +257,7 @@ class Packet : public FastAlloc, public Printable
Addr addr;
/// The size of the request or transfer.
- int size;
+ unsigned size;
/**
* Device address (e.g., bus ID) of the source of the
@@ -450,7 +450,7 @@ class Packet : public FastAlloc, public Printable
void setDest(NodeID _dest) { dest = _dest; flags.set(VALID_DST); }
Addr getAddr() const { assert(flags.isSet(VALID_ADDR)); return addr; }
- int getSize() const { assert(flags.isSet(VALID_SIZE)); return size; }
+ unsigned getSize() const { assert(flags.isSet(VALID_SIZE)); return size; }
Addr getOffset(int blkSize) const { return getAddr() & (Addr)(blkSize - 1); }
/**
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index bdcbbfec3..bf35932a6 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -189,7 +189,7 @@ PageTable::serialize(std::ostream &os)
{
paramOut(os, "ptable.size", pTable.size());
- int count = 0;
+ PTable::size_type count = 0;
PTableItr iter = pTable.begin();
PTableItr end = pTable.end();
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index a49c12a5c..e6150c548 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -106,8 +106,8 @@ PhysicalMemory::new_page()
return return_addr;
}
-int
-PhysicalMemory::deviceBlockSize()
+unsigned
+PhysicalMemory::deviceBlockSize() const
{
//Can accept anysize request
return 0;
@@ -360,8 +360,8 @@ PhysicalMemory::getPort(const std::string &if_name, int idx)
panic("PhysicalMemory::getPort: unknown port %s requested", if_name);
}
- if (idx >= ports.size()) {
- ports.resize(idx+1);
+ if (idx >= (int)ports.size()) {
+ ports.resize(idx + 1);
}
if (ports[idx] != NULL) {
@@ -407,8 +407,8 @@ PhysicalMemory::getAddressRanges(AddrRangeList &resp, bool &snoop)
resp.push_back(RangeSize(start(), params()->range.size()));
}
-int
-PhysicalMemory::MemoryPort::deviceBlockSize()
+unsigned
+PhysicalMemory::MemoryPort::deviceBlockSize() const
{
return memory->deviceBlockSize();
}
@@ -474,7 +474,7 @@ PhysicalMemory::serialize(ostream &os)
filename);
if (gzwrite(compressedMem, pmemAddr, params()->range.size()) !=
- params()->range.size()) {
+ (int)params()->range.size()) {
fatal("Write failed on physical memory checkpoint file '%s'\n",
filename);
}
@@ -495,7 +495,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
long *pmem_current;
uint64_t curSize;
uint32_t bytesRead;
- const int chunkSize = 16384;
+ const uint32_t chunkSize = 16384;
string filename;
@@ -545,7 +545,7 @@ PhysicalMemory::unserialize(Checkpoint *cp, const string &section)
assert(bytesRead % sizeof(long) == 0);
- for (int x = 0; x < bytesRead/sizeof(long); x++)
+ for (uint32_t x = 0; x < bytesRead / sizeof(long); x++)
{
if (*(tempPage+x) != 0) {
pmem_current = (long*)(pmemAddr + curSize + x * sizeof(long));
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index f027168a4..dae6b42af 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -70,7 +70,7 @@ class PhysicalMemory : public MemObject
virtual void getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop);
- virtual int deviceBlockSize();
+ virtual unsigned deviceBlockSize() const;
};
int numPorts;
@@ -168,7 +168,7 @@ class PhysicalMemory : public MemObject
}
public:
- int deviceBlockSize();
+ unsigned deviceBlockSize() const;
void getAddressRanges(AddrRangeList &resp, bool &snoop);
virtual Port *getPort(const std::string &if_name, int idx = -1);
void virtual init();
diff --git a/src/mem/port.cc b/src/mem/port.cc
index a666c968b..4d44d486d 100644
--- a/src/mem/port.cc
+++ b/src/mem/port.cc
@@ -42,7 +42,7 @@
class DefaultPeerPort : public Port
{
protected:
- void blowUp()
+ void blowUp() const
{
fatal("%s: Unconnected port!", peer->name());
}
@@ -74,7 +74,8 @@ class DefaultPeerPort : public Port
blowUp();
}
- int deviceBlockSize()
+ unsigned
+ deviceBlockSize() const
{
blowUp();
return 0;
diff --git a/src/mem/port.hh b/src/mem/port.hh
index e738cfc63..bb74bf497 100644
--- a/src/mem/port.hh
+++ b/src/mem/port.hh
@@ -161,7 +161,7 @@ class Port : public EventManager
this function to be called, so it just returns 0. Anytthing that is
concerned with the size should just ignore that.
*/
- virtual int deviceBlockSize() { return 0; }
+ virtual unsigned deviceBlockSize() const { return 0; }
/** The peer port is requesting us to reply with a list of the ranges we
are responsible for.
@@ -214,7 +214,7 @@ class Port : public EventManager
/** Called by the associated device if it wishes to find out the blocksize
of the device on attached to the peer port.
*/
- int peerBlockSize() { return peer->deviceBlockSize(); }
+ unsigned peerBlockSize() const { return peer->deviceBlockSize(); }
/** Called by the associated device if it wishes to find out the address
ranges connected to the peer ports devices.
diff --git a/src/mem/rubymem.cc b/src/mem/rubymem.cc
index 3f121f7af..83bac2fd5 100644
--- a/src/mem/rubymem.cc
+++ b/src/mem/rubymem.cc
@@ -153,7 +153,7 @@ RubyMemory::getPort(const std::string &if_name, int idx)
panic("RubyMemory::getPort: unknown port %s requested", if_name);
}
- if (idx >= ports.size()) {
+ if (idx >= (int)ports.size()) {
ports.resize(idx+1);
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-02 22:39:20 +0000