7 files changed, 14 insertions, 15 deletions

diff --git a/src/mem/abstract_mem.hh b/src/mem/abstract_mem.hh
index 4b7ad8139..6dbc79ea0 100644
--- a/src/mem/abstract_mem.hh
+++ b/src/mem/abstract_mem.hh
@@ -74,7 +74,7 @@ class LockedAddr {
     Addr addr;
 
     // locking hw context
-    const int contextId;
+    const ContextID contextId;
 
     static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
 
diff --git a/src/mem/cache/blk.hh b/src/mem/cache/blk.hh
index 0be22f45d..2b3a34bb8 100644
--- a/src/mem/cache/blk.hh
+++ b/src/mem/cache/blk.hh
@@ -130,7 +130,7 @@ class CacheBlk
      */
     class Lock {
       public:
-        int contextId;     // locking context
+        ContextID contextId;     // locking context
         Addr lowAddr;      // low address of lock range
         Addr highAddr;     // high address of lock range
 
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 62ab49538..dea95d955 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -332,7 +332,8 @@ Cache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
         return false;
     }
 
-    int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1;
+    ContextID id = pkt->req->hasContextId() ?
+        pkt->req->contextId() : InvalidContextID;
     // Here lat is the value passed as parameter to accessBlock() function
     // that can modify its value.
     blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id);
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index d757b8c5d..dfea2e9e1 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -293,7 +293,7 @@ PhysicalMemory::serialize(CheckpointOut &cp) const
 {
     // serialize all the locked addresses and their context ids
     vector<Addr> lal_addr;
-    vector<int> lal_cid;
+    vector<ContextID> lal_cid;
 
     for (auto& m : memories) {
         const list<LockedAddr>& locked_addrs = m->getLockedAddrList();
@@ -370,7 +370,7 @@ PhysicalMemory::unserialize(CheckpointIn &cp)
     // unserialize the locked addresses and map them to the
     // appropriate memory controller
     vector<Addr> lal_addr;
-    vector<int> lal_cid;
+    vector<ContextID> lal_cid;
     UNSERIALIZE_CONTAINER(lal_addr);
     UNSERIALIZE_CONTAINER(lal_cid);
     for(size_t i = 0; i < lal_addr.size(); ++i) {
diff --git a/src/mem/request.hh b/src/mem/request.hh
index 192b4c89f..0e2ece857 100644
--- a/src/mem/request.hh
+++ b/src/mem/request.hh
@@ -296,7 +296,7 @@ class Request
     uint64_t _extraData;
 
     /** The context ID (for statistics, typically). */
-    int _contextId;
+    ContextID _contextId;
     /** The thread ID (id within this CPU) */
     ThreadID _threadId;
 
@@ -353,7 +353,7 @@ class Request
     }
 
     Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid,
-            Addr pc, int cid, ThreadID tid)
+            Addr pc, ContextID cid, ThreadID tid)
         : _paddr(0), _size(0), _masterId(invldMasterId), _time(0),
           _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0),
           _extraData(0), _contextId(0), _threadId(0), _pc(0),
@@ -369,7 +369,7 @@ class Request
      * Set up CPU and thread numbers.
      */
     void
-    setThreadContext(int context_id, ThreadID tid)
+    setThreadContext(ContextID context_id, ThreadID tid)
     {
         _contextId = context_id;
         _threadId = tid;
@@ -591,7 +591,7 @@ class Request
     }
 
     /** Accessor function for context ID.*/
-    int
+    ContextID
     contextId() const
     {
         assert(privateFlags.isSet(VALID_CONTEXT_ID));
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
index 357eddbb5..cdb04bceb 100644
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -49,12 +49,12 @@ class RubyRequest : public Message
     PrefetchBit m_Prefetch;
     uint8_t* data;
     PacketPtr pkt;
-    unsigned m_contextId;
+    ContextID m_contextId;
 
     RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len,
         uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode,
         PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No,
-        unsigned _proc_id = 100)
+        ContextID _proc_id = 100)
         : Message(curTime),
           m_PhysicalAddress(_paddr),
           m_Type(_type),
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 32e4c107c..01b868017 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -667,10 +667,8 @@ void
 Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type)
 {
     assert(pkt != NULL);
-    int proc_id = -1;
-    if (pkt->req->hasContextId()) {
-        proc_id = pkt->req->contextId();
-    }
+    ContextID proc_id = pkt->req->hasContextId() ?
+        pkt->req->contextId() : InvalidContextID;
 
     // If valid, copy the pc to the ruby request
     Addr pc = 0;