diff options
Diffstat (limited to 'src/mem')
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dir.sm | 15 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_directory-dma.sm | 17 | ||||
-rw-r--r-- | src/mem/protocol/MOESI_CMP_token-L2cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm | 2 | ||||
-rw-r--r-- | src/mem/protocol/RubySlicc_Util.sm | 1 | ||||
-rw-r--r-- | src/mem/ruby/config/cfg.rb | 6 | ||||
-rw-r--r-- | src/mem/ruby/config/defaults.rb | 4 | ||||
-rw-r--r-- | src/mem/ruby/network/Network.cc | 39 | ||||
-rw-r--r-- | src/mem/ruby/network/Network.hh | 41 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/simple/Switch.cc | 2 | ||||
-rw-r--r-- | src/mem/ruby/network/simple/Throttle.cc | 4 | ||||
-rw-r--r-- | src/mem/ruby/slicc_interface/RubySlicc_Util.hh | 5 |
14 files changed, 72 insertions, 70 deletions
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm index edd67707e..8d8ee7f8a 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm @@ -101,7 +101,7 @@ machine(Directory, "Directory protocol") } structure(TBE, desc="...") { - Address address, desc="Address for this entry"; + Address PhysicalAddress, desc="Physical address for this entry"; int Len, desc="Length of request"; DataBlock DataBlk, desc="DataBlk"; MachineID Requestor, desc="original requestor"; @@ -245,9 +245,9 @@ machine(Directory, "Directory protocol") } else if (in_msg.Type == CoherenceRequestType:PUTO_SHARERS) { trigger(Event:PUTO_SHARERS, in_msg.Address); } else if (in_msg.Type == CoherenceRequestType:DMA_READ) { - trigger(Event:DMA_READ, in_msg.Address); + trigger(Event:DMA_READ, makeLineAddress(in_msg.Address)); } else if (in_msg.Type == CoherenceRequestType:DMA_WRITE) { - trigger(Event:DMA_WRITE, in_msg.Address); + trigger(Event:DMA_WRITE, makeLineAddress(in_msg.Address)); } else { error("Invalid message"); } @@ -527,12 +527,15 @@ machine(Directory, "Directory protocol") } action(l_writeDMADataToMemoryFromTBE, "\ll", desc="Write data from a DMA_WRITE to memory") { - directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, addressOffset(address), TBEs[address].Len); + directory[address].DataBlk.copyPartial(TBEs[address].DataBlk, + addressOffset(TBEs[address].PhysicalAddress), + TBEs[address].Len); } action(v_allocateTBE, "v", desc="Allocate TBE entry") { peek (requestQueue_in, RequestMsg) { TBEs.allocate(address); + TBEs[address].PhysicalAddress := in_msg.Address; TBEs[address].Len := in_msg.Len; TBEs[address].DataBlk := in_msg.DataBlk; TBEs[address].Requestor := in_msg.Requestor; @@ -695,7 +698,7 @@ machine(Directory, "Directory protocol") } - transition({MM, MO, MI, MIS, OS, OSS}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) { + transition({MM, MO, MI, MIS, OS, OSS, XI_M, XI_U, OI_D}, {GETS, GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) { zz_recycleRequest; } @@ -710,7 +713,7 @@ machine(Directory, "Directory protocol") j_popIncomingUnblockQueue; } - transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ}) { + transition({IS, SS, OO}, {GETX, PUTO, PUTO_SHARERS, PUTX, DMA_READ, DMA_WRITE}) { zz_recycleRequest; } diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm index 74246c730..ae86e24da 100644 --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm @@ -83,9 +83,9 @@ machine(DMA, "DMA Controller") if (dmaRequestQueue_in.isReady()) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { - trigger(Event:ReadRequest, in_msg.PhysicalAddress); + trigger(Event:ReadRequest, in_msg.LineAddress); } else if (in_msg.Type == SequencerRequestType:ST) { - trigger(Event:WriteRequest, in_msg.PhysicalAddress); + trigger(Event:WriteRequest, in_msg.LineAddress); } else { error("Invalid request type"); } @@ -97,11 +97,12 @@ machine(DMA, "DMA Controller") if (dmaResponseQueue_in.isReady()) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:DMA_ACK) { - trigger(Event:DMA_Ack, in_msg.Address); - } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE) { - trigger(Event:Data, in_msg.Address); + trigger(Event:DMA_Ack, makeLineAddress(in_msg.Address)); + } else if (in_msg.Type == CoherenceResponseType:DATA_EXCLUSIVE || + in_msg.Type == CoherenceResponseType:DATA) { + trigger(Event:Data, makeLineAddress(in_msg.Address)); } else if (in_msg.Type == CoherenceResponseType:ACK) { - trigger(Event:Inv_Ack, in_msg.Address); + trigger(Event:Inv_Ack, makeLineAddress(in_msg.Address)); } else { error("Invalid response type"); } @@ -125,7 +126,7 @@ machine(DMA, "DMA Controller") action(s_sendReadRequest, "s", desc="Send a DMA read request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := address; + out_msg.Address := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_READ; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; @@ -139,7 +140,7 @@ machine(DMA, "DMA Controller") action(s_sendWriteRequest, "\s", desc="Send a DMA write request to memory") { peek(dmaRequestQueue_in, SequencerMsg) { enqueue(reqToDirectory_out, RequestMsg, latency=request_latency) { - out_msg.Address := address; + out_msg.Address := in_msg.PhysicalAddress; out_msg.Type := CoherenceRequestType:DMA_WRITE; out_msg.DataBlk := in_msg.DataBlk; out_msg.Len := in_msg.Len; diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm index 21fbf0b95..0a58ed5cf 100644 --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm @@ -916,7 +916,7 @@ machine(L2Cache, "Token protocol") { action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(L1requestNetwork_in, RequestMsg) { // AccessModeType not implemented - profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); + //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, machineIDToNodeID(in_msg.Requestor)); } } diff --git a/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm b/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm index d68efc819..9f85e3a8f 100644 --- a/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm +++ b/src/mem/protocol/MSI_MOSI_CMP_directory-L2cache.sm @@ -978,7 +978,7 @@ machine(L2Cache, "MOSI Directory L2 Cache CMP") { action(uu_profileMiss, "\u", desc="Profile the demand miss") { peek(L1RequestIntraChipL2Network_in, RequestMsg) { - profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.RequestorMachId)); + //profile_L2Cache_miss(convertToGenericType(in_msg.Type), in_msg.AccessMode, MessageSizeTypeToInt(in_msg.MessageSize), in_msg.Prefetch, L1CacheMachIDToProcessorNum(in_msg.RequestorMachId)); } } diff --git a/src/mem/protocol/RubySlicc_Util.sm b/src/mem/protocol/RubySlicc_Util.sm index b37725402..312682bd7 100644 --- a/src/mem/protocol/RubySlicc_Util.sm +++ b/src/mem/protocol/RubySlicc_Util.sm @@ -37,7 +37,6 @@ Time zero_time(); NodeID intToID(int nodenum); int IDToInt(NodeID id); int addressToInt(Address addr); -int MessageSizeTypeToInt(MessageSizeType size_type); bool multicast_retry(); int numberOfNodes(); int numberOfL1CachePerChip(); diff --git a/src/mem/ruby/config/cfg.rb b/src/mem/ruby/config/cfg.rb index ffc36dd67..445bb4885 100644 --- a/src/mem/ruby/config/cfg.rb +++ b/src/mem/ruby/config/cfg.rb @@ -11,7 +11,7 @@ end def assert(condition,message) unless condition - raise AssertionFailure, "Assertion failed: #{message}" + raise AssertionFailure, "\n\nAssertion failed: \n\n #{message}\n\n" end end @@ -309,7 +309,7 @@ class CacheController < NetPort cache.controller = self } - if !@@total_cache_controllers.has_key?(mach_type) + if !@@total_cache_controllers.key?(mach_type) @@total_cache_controllers[mach_type] = 0 end @version = @@total_cache_controllers[mach_type] @@ -631,7 +631,7 @@ class Network < LibRubyObject vec += " buffer_size "+buffer_size.to_s vec += " link_latency "+adaptive_routing.to_s vec += " on_chip_latency "+on_chip_latency.to_s - + vec += " control_msg_size "+control_msg_size.to_s end def printTopology() diff --git a/src/mem/ruby/config/defaults.rb b/src/mem/ruby/config/defaults.rb index 4723df505..384abd119 100644 --- a/src/mem/ruby/config/defaults.rb +++ b/src/mem/ruby/config/defaults.rb @@ -39,7 +39,7 @@ class Debug < LibRubyObject default_param :protocol_trace, Boolean, false # a string for filtering debugging output (for all g_debug vars see Debug.h) - default_param :filter_string, String, "" + default_param :filter_string, String, "none" # filters debugging messages based on priority (low, med, high) default_param :verbosity_string, String, "none" @@ -82,6 +82,8 @@ class Network < LibRubyObject # on chip latency default_param :on_chip_latency, Integer, 1 + + default_param :control_msg_size, Integer, 8 end class GarnetNetwork < Network diff --git a/src/mem/ruby/network/Network.cc b/src/mem/ruby/network/Network.cc index cb3507471..984ec7ca8 100644 --- a/src/mem/ruby/network/Network.cc +++ b/src/mem/ruby/network/Network.cc @@ -26,9 +26,44 @@ void Network::init(const vector<string> & argv) m_adaptive_routing = (argv[i+1]=="true"); else if (argv[i] == "link_latency") m_link_latency = atoi(argv[i+1].c_str()); - + else if (argv[i] == "control_msg_size") + m_control_msg_size = atoi(argv[i+1].c_str()); } + + m_data_msg_size = RubySystem::getBlockSizeBytes() + m_control_msg_size; + assert(m_virtual_networks != 0); assert(m_topology_ptr != NULL); -// printf ("HERE \n"); +} + +int Network::MessageSizeType_to_int(MessageSizeType size_type) +{ + switch(size_type) { + case MessageSizeType_Undefined: + ERROR_MSG("Can't convert Undefined MessageSizeType to integer"); + break; + case MessageSizeType_Control: + case MessageSizeType_Request_Control: + case MessageSizeType_Reissue_Control: + case MessageSizeType_Response_Control: + case MessageSizeType_Writeback_Control: + case MessageSizeType_Forwarded_Control: + case MessageSizeType_Invalidate_Control: + case MessageSizeType_Unblock_Control: + case MessageSizeType_Persistent_Control: + case MessageSizeType_Completion_Control: + return m_control_msg_size; + break; + case MessageSizeType_Data: + case MessageSizeType_Response_Data: + case MessageSizeType_ResponseLocal_Data: + case MessageSizeType_ResponseL2hit_Data: + case MessageSizeType_Writeback_Data: + return m_data_msg_size; + break; + default: + ERROR_MSG("Invalid range for type MessageSizeType"); + break; + } + return 0; } diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh index 17fbaab22..e7c86b6b2 100644 --- a/src/mem/ruby/network/Network.hh +++ b/src/mem/ruby/network/Network.hh @@ -71,6 +71,8 @@ public: int getEndpointBandwidth() { return m_endpoint_bandwidth; } bool getAdaptiveRouting() {return m_adaptive_routing; } int getLinkLatency() { return m_link_latency; } + int MessageSizeType_to_int(MessageSizeType size_type); + // returns the queue requested for the given component virtual MessageBuffer* getToNetQueue(NodeID id, bool ordered, int netNumber) = 0; @@ -107,6 +109,8 @@ protected: Topology* m_topology_ptr; bool m_adaptive_routing; int m_link_latency; + int m_control_msg_size; + int m_data_msg_size; }; // Output operator declaration @@ -123,41 +127,4 @@ ostream& operator<<(ostream& out, const Network& obj) return out; } -// Code to map network message size types to an integer number of bytes -const int CONTROL_MESSAGE_SIZE = 8; -const int DATA_MESSAGE_SIZE = (RubySystem::getBlockSizeBytes()+8); - -extern inline -int MessageSizeType_to_int(MessageSizeType size_type) -{ - switch(size_type) { - case MessageSizeType_Undefined: - ERROR_MSG("Can't convert Undefined MessageSizeType to integer"); - break; - case MessageSizeType_Control: - case MessageSizeType_Request_Control: - case MessageSizeType_Reissue_Control: - case MessageSizeType_Response_Control: - case MessageSizeType_Writeback_Control: - case MessageSizeType_Forwarded_Control: - case MessageSizeType_Invalidate_Control: - case MessageSizeType_Unblock_Control: - case MessageSizeType_Persistent_Control: - case MessageSizeType_Completion_Control: - return CONTROL_MESSAGE_SIZE; - break; - case MessageSizeType_Data: - case MessageSizeType_Response_Data: - case MessageSizeType_ResponseLocal_Data: - case MessageSizeType_ResponseL2hit_Data: - case MessageSizeType_Writeback_Data: - return DATA_MESSAGE_SIZE; - break; - default: - ERROR_MSG("Invalid range for type MessageSizeType"); - break; - } - return 0; -} - #endif //NETWORK_H diff --git a/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc index f75997757..3377ffd1d 100644 --- a/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc +++ b/src/mem/ruby/network/garnet-fixed-pipeline/NetworkInterface_d.cc @@ -114,7 +114,7 @@ bool NetworkInterface_d::flitisizeMessage(MsgPtr msg_ptr, int vnet) NetDest net_msg_dest = net_msg_ptr->getInternalDestination(); Vector<NodeID> dest_nodes = net_msg_dest.getAllDest(); // gets all the destinations associated with this message. - int num_flits = (int) ceil((double) MessageSizeType_to_int(net_msg_ptr->getMessageSize())/m_net_ptr->getNetworkConfig()->getFlitSize() ); // Number of flits is dependent on the link bandwidth available. This is expressed in terms of bytes/cycle or the flit size + int num_flits = (int) ceil((double) m_net_ptr->MessageSizeType_to_int(net_msg_ptr->getMessageSize())/m_net_ptr->getNetworkConfig()->getFlitSize() ); // Number of flits is dependent on the link bandwidth available. This is expressed in terms of bytes/cycle or the flit size for(int ctr = 0; ctr < dest_nodes.size(); ctr++) // loop because we will be converting all multicast messages into unicast messages { diff --git a/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc index 119f064d3..597c942b7 100644 --- a/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc +++ b/src/mem/ruby/network/garnet-flexible-pipeline/NetworkInterface.cc @@ -109,7 +109,7 @@ bool NetworkInterface::flitisizeMessage(MsgPtr msg_ptr, int vnet) NetworkMessage *net_msg_ptr = dynamic_cast<NetworkMessage*>(msg_ptr.ref()); NetDest net_msg_dest = net_msg_ptr->getInternalDestination(); Vector<NodeID> dest_nodes = net_msg_dest.getAllDest(); // gets all the destinations associated with this message. - int num_flits = (int) ceil((double) MessageSizeType_to_int(net_msg_ptr->getMessageSize())/m_net_ptr->getNetworkConfig()->getFlitSize() ); // Number of flits is dependent on the link bandwidth available. This is expressed in terms of bytes/cycle or the flit size + int num_flits = (int) ceil((double) m_net_ptr->MessageSizeType_to_int(net_msg_ptr->getMessageSize())/m_net_ptr->getNetworkConfig()->getFlitSize() ); // Number of flits is dependent on the link bandwidth available. This is expressed in terms of bytes/cycle or the flit size for(int ctr = 0; ctr < dest_nodes.size(); ctr++) // loop because we will be converting all multicast messages into unicast messages { diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc index e3420ddae..87021471f 100644 --- a/src/mem/ruby/network/simple/Switch.cc +++ b/src/mem/ruby/network/simple/Switch.cc @@ -169,7 +169,7 @@ void Switch::printStats(ostream& out) const int sum = message_counts[type].sum(); if (sum != 0) { out << " outgoing_messages_switch_" << m_switch_id << "_link_" << link << "_" << type - << ": " << sum << " " << sum * MessageSizeType_to_int(type) + << ": " << sum << " " << sum * (RubySystem::getNetwork()->MessageSizeType_to_int(type)) << " " << message_counts[type] << " base_latency: " << throttle_ptr->getLatency() << endl; } } diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc index 64cb2a33a..89d61f267 100644 --- a/src/mem/ruby/network/simple/Throttle.cc +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -275,8 +275,8 @@ int network_message_to_size(NetworkMessage* net_msg_ptr) // Artificially increase the size of broadcast messages if (BROADCAST_SCALING > 1) { if (net_msg_ptr->getDestination().isBroadcast()) { - return (MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER * BROADCAST_SCALING); + return (RubySystem::getNetwork()->MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER * BROADCAST_SCALING); } } - return (MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER); + return (RubySystem::getNetwork()->MessageSizeType_to_int(net_msg_ptr->getMessageSize()) * MESSAGE_SIZE_MULTIPLIER); } diff --git a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh index 0ea5df08b..3d4fa3e5c 100644 --- a/src/mem/ruby/slicc_interface/RubySlicc_Util.hh +++ b/src/mem/ruby/slicc_interface/RubySlicc_Util.hh @@ -106,11 +106,6 @@ extern inline int addressToInt(Address addr) return (int) addr.getLineAddress(); } -extern inline int MessageSizeTypeToInt(MessageSizeType size_type) -{ - return MessageSizeType_to_int(size_type); -} - extern inline bool long_enough_ago(Time event) { return ((get_time() - event) > 200); |