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-rw-r--r--src/mem/cache/prefetch/stride.cc1
-rw-r--r--src/mem/external_master.cc1
-rw-r--r--src/mem/external_slave.cc1
-rw-r--r--src/mem/mem_checker.hh1
-rw-r--r--src/mem/multi_level_page_table.hh5
-rw-r--r--src/mem/multi_level_page_table_impl.hh9
-rw-r--r--src/mem/page_table.cc7
-rw-r--r--src/mem/page_table.hh3
-rw-r--r--src/mem/ruby/network/MessageBuffer.hh1
-rw-r--r--src/mem/ruby/structures/AbstractReplacementPolicy.cc2
-rw-r--r--src/mem/se_translating_port_proxy.hh2
-rw-r--r--src/mem/simple_mem.cc1
12 files changed, 17 insertions, 17 deletions
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index e9c83f2ff..f2679a292 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -49,6 +49,7 @@
#include "mem/cache/prefetch/stride.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/HWPrefetch.hh"
StridePrefetcher::StridePrefetcher(const StridePrefetcherParams *p)
diff --git a/src/mem/external_master.cc b/src/mem/external_master.cc
index 94fdc39cf..143019950 100644
--- a/src/mem/external_master.cc
+++ b/src/mem/external_master.cc
@@ -43,6 +43,7 @@
#include <cctype>
#include <iomanip>
+#include "base/trace.hh"
#include "debug/ExternalPort.hh"
std::map<std::string, ExternalMaster::Handler *>
diff --git a/src/mem/external_slave.cc b/src/mem/external_slave.cc
index 2d7ba1a65..990e3561a 100644
--- a/src/mem/external_slave.cc
+++ b/src/mem/external_slave.cc
@@ -42,6 +42,7 @@
#include <cctype>
#include <iomanip>
+#include "base/trace.hh"
#include "debug/ExternalPort.hh"
/** Implement a `stub' port which just responds to requests by printing
diff --git a/src/mem/mem_checker.hh b/src/mem/mem_checker.hh
index 6ceca74a7..7de4c17b7 100644
--- a/src/mem/mem_checker.hh
+++ b/src/mem/mem_checker.hh
@@ -48,6 +48,7 @@
#include <vector>
#include "base/misc.hh"
+#include "base/trace.hh"
#include "base/types.hh"
#include "debug/MemChecker.hh"
#include "params/MemChecker.hh"
diff --git a/src/mem/multi_level_page_table.hh b/src/mem/multi_level_page_table.hh
index a1d3fbc39..a69d6ce7f 100644
--- a/src/mem/multi_level_page_table.hh
+++ b/src/mem/multi_level_page_table.hh
@@ -38,13 +38,12 @@
#include <string>
-#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/page_table.hh"
-#include "sim/serialize.hh"
-#include "sim/system.hh"
+
+class System;
/**
* This class implements an in-memory multi-level page table that can be
diff --git a/src/mem/multi_level_page_table_impl.hh b/src/mem/multi_level_page_table_impl.hh
index 610240562..07ac92406 100644
--- a/src/mem/multi_level_page_table_impl.hh
+++ b/src/mem/multi_level_page_table_impl.hh
@@ -32,18 +32,15 @@
* @file
* Definitions of page table
*/
-#include <fstream>
-#include <map>
#include <string>
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
+#include "arch/isa_traits.hh"
+#include "arch/tlb.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "mem/multi_level_page_table.hh"
-#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "mem/page_table.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index f47227f5a..8ff640837 100644
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -37,18 +37,13 @@
*/
#include "mem/page_table.hh"
-#include <fstream>
-#include <map>
-#include <memory>
#include <string>
-#include "base/bitfield.hh"
-#include "base/intmath.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
#include "debug/MMU.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/serialize.hh"
using namespace std;
using namespace TheISA;
diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 645548263..9b24c0efa 100644
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -42,13 +42,14 @@
#include "arch/isa_traits.hh"
#include "arch/tlb.hh"
+#include "base/intmath.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/serialize.hh"
-#include "sim/system.hh"
class ThreadContext;
+class System;
/**
* Declaration of base class for page table
diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh
index e6ec5ac4b..6694830b0 100644
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -41,6 +41,7 @@
#include <string>
#include <vector>
+#include "base/trace.hh"
#include "debug/RubyQueue.hh"
#include "mem/ruby/common/Address.hh"
#include "mem/ruby/common/Consumer.hh"
diff --git a/src/mem/ruby/structures/AbstractReplacementPolicy.cc b/src/mem/ruby/structures/AbstractReplacementPolicy.cc
index 5abd55083..05304dc84 100644
--- a/src/mem/ruby/structures/AbstractReplacementPolicy.cc
+++ b/src/mem/ruby/structures/AbstractReplacementPolicy.cc
@@ -30,6 +30,8 @@
#include "mem/ruby/structures/AbstractReplacementPolicy.hh"
+#include "base/misc.hh"
+
AbstractReplacementPolicy::AbstractReplacementPolicy(const Params * p)
: SimObject(p)
{
diff --git a/src/mem/se_translating_port_proxy.hh b/src/mem/se_translating_port_proxy.hh
index 58d0c9bcd..bb823a75b 100644
--- a/src/mem/se_translating_port_proxy.hh
+++ b/src/mem/se_translating_port_proxy.hh
@@ -45,9 +45,9 @@
#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
-#include "mem/page_table.hh"
#include "mem/port_proxy.hh"
+class PageTableBase;
class Process;
/**
diff --git a/src/mem/simple_mem.cc b/src/mem/simple_mem.cc
index f3a01b5b0..f524d01ab 100644
--- a/src/mem/simple_mem.cc
+++ b/src/mem/simple_mem.cc
@@ -45,6 +45,7 @@
#include "mem/simple_mem.hh"
#include "base/random.hh"
+#include "base/trace.hh"
#include "debug/Drain.hh"
using namespace std;