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Diffstat (limited to 'src/python/m5/objects/BaseCPU.py')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 88a8bf5e3..41e90b12b 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -6,7 +6,7 @@ from Bus import Bus class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject(Parent.any, "memory") + mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") if build_env['FULL_SYSTEM']: |