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-rw-r--r--src/python/m5/objects/BaseCPU.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 7906156a2..01458aeb4 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -49,5 +49,5 @@ class BaseCPU(SimObject):
self.toL2Bus = Bus()
self.connectMemPorts(self.toL2Bus)
self.l2cache = l2c
- self.l2cache.cpu_side = toL2Bus.port
+ self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']