diff options
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/Root.py | 2 | ||||
| -rw-r--r-- | src/python/m5/objects/T1000.py | 5 |
2 files changed, 4 insertions, 3 deletions
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index 81482c1de..c78ae6ccb 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -3,7 +3,6 @@ from m5.params import * from Serialize import Serialize from Serialize import Statreset from Statistics import Statistics -from ExeTrace import ExecutionTrace class Root(SimObject): type = 'Root' @@ -16,5 +15,4 @@ class Root(SimObject): # stats = Param.Statistics(Statistics(), "statistics object") # serialize = Param.Serialize(Serialize(), "checkpoint generation options") stats = Statistics() - exetrace = ExecutionTrace() serialize = Serialize() diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py index 85c4db6df..3ab6d4283 100644 --- a/src/python/m5/objects/T1000.py +++ b/src/python/m5/objects/T1000.py @@ -69,16 +69,19 @@ class T1000(Platform): fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) #warn_access="Accessing SSI -- Unimplemented!") + hconsole = SimConsole(listener = ConsoleListener()) hvuart = Uart8250(pio_addr=0xfff0c2c000) htod = DumbTOD() + pconsole = SimConsole(listener = ConsoleListener()) puart0 = Uart8250(pio_addr=0x1f10000000) - console = SimConsole(listener = ConsoleListener()) # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. def attachIO(self, bus): + self.hvuart.sim_console = self.hconsole + self.puart0.sim_console = self.pconsole self.fake_clk.pio = bus.port self.fake_membnks.pio = bus.port self.fake_iob.pio = bus.port |