diff options
Diffstat (limited to 'src/python/m5/objects')
| -rw-r--r-- | src/python/m5/objects/BaseCPU.py | 15 | ||||
| -rw-r--r-- | src/python/m5/objects/Bus.py | 10 | ||||
| -rw-r--r-- | src/python/m5/objects/Pci.py | 3 | ||||
| -rw-r--r-- | src/python/m5/objects/SparcTLB.py | 14 | ||||
| -rw-r--r-- | src/python/m5/objects/System.py | 19 | ||||
| -rw-r--r-- | src/python/m5/objects/Tsunami.py | 7 |
6 files changed, 60 insertions, 8 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index b6dc08e46..b6e05627d 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -3,19 +3,27 @@ from m5.params import * from m5.proxy import * from m5 import build_env from AlphaTLB import AlphaDTB, AlphaITB +from SparcTLB import SparcDTB, SparcITB from Bus import Bus +import sys class BaseCPU(SimObject): type = 'BaseCPU' abstract = True - mem = Param.MemObject("memory") system = Param.System(Parent.any, "system object") cpu_id = Param.Int("CPU identifier") if build_env['FULL_SYSTEM']: - dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") - itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") + if build_env['TARGET_ISA'] == 'sparc': + dtb = Param.SparcDTB(SparcDTB(), "Data TLB") + itb = Param.SparcITB(SparcITB(), "Instruction TLB") + elif build_env['TARGET_ISA'] == 'alpha': + dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB") + itb = Param.AlphaITB(AlphaITB(), "Instruction TLB") + else: + print "Unknown architecture, can't pick TLBs" + sys.exit(1) else: workload = VectorParam.Process("processes to run") @@ -47,7 +55,6 @@ class BaseCPU(SimObject): self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] -# self.mem = dc def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index 6710111e5..e7019f3ac 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -1,10 +1,18 @@ +from m5 import build_env from m5.params import * +from m5.proxy import * from MemObject import MemObject +from Tsunami import BadAddr class Bus(MemObject): type = 'Bus' port = VectorPort("vector port for connecting devices") - default = Port("Default port for requests that aren't handeled by a device.") bus_id = Param.Int(0, "blah") clock = Param.Clock("1GHz", "bus clock speed") width = Param.Int(64, "bus width (bytes)") + responder_set = Param.Bool(False, "Did the user specify a default responder.") + if build_env['FULL_SYSTEM']: + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") + responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + else: + default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py index 55bf23534..9d40adbfe 100644 --- a/src/python/m5/objects/Pci.py +++ b/src/python/m5/objects/Pci.py @@ -57,6 +57,3 @@ class PciDevice(DmaDevice): pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") configdata = Param.PciConfigData(Parent.any, "PCI Config data") config_latency = Param.Latency('20ns', "Config read or write latency") - -class PciFake(PciDevice): - type = 'PciFake' diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py new file mode 100644 index 000000000..de732e8de --- /dev/null +++ b/src/python/m5/objects/SparcTLB.py @@ -0,0 +1,14 @@ +from m5.SimObject import SimObject +from m5.params import * +class SparcTLB(SimObject): + type = 'SparcTLB' + abstract = True + size = Param.Int("TLB size") + +class SparcDTB(SparcTLB): + type = 'SparcDTB' + size = 64 + +class SparcITB(SparcTLB): + type = 'SparcITB' + size = 48 diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py index e7dd1bc60..908c3d4ad 100644 --- a/src/python/m5/objects/System.py +++ b/src/python/m5/objects/System.py @@ -2,6 +2,7 @@ from m5.SimObject import SimObject from m5.params import * from m5.proxy import * from m5 import build_env +from PhysicalMemory import * class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] @@ -24,3 +25,21 @@ class AlphaSystem(System): pal = Param.String("file that contains palcode") system_type = Param.UInt64("Type of system we are emulating") system_rev = Param.UInt64("Revision of system we are emulating") + +class SparcSystem(System): + type = 'SparcSystem' + _rom_base = 0xfff0000000 + # ROM for OBP/Reset/Hypervisor + rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')), + "Memory to hold the ROM data") + + reset_addr = Param.Addr(_rom_base, "Address to load ROM at") + hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, + "Address to load hypervisor at") + openboot_addr = Param.Addr(Addr('512kB') + _rom_base, + "Address to load openboot at") + + reset_bin = Param.String("file that contains the reset code") + hypervisor_bin = Param.String("file that contains the hypervisor code") + openboot_bin = Param.String("file that contains the openboot code") + diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 0b53153a0..ffe93727b 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -14,6 +14,11 @@ class TsunamiCChip(BasicPioDevice): class IsaFake(BasicPioDevice): type = 'IsaFake' pio_size = Param.Addr(0x8, "Size of address range") + ret_data = Param.UInt8(0xFF, "Default data to return") + ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") + +class BadAddr(IsaFake): + ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' @@ -70,6 +75,8 @@ class Tsunami(Platform): self.cchip.pio = bus.port self.pchip.pio = bus.port self.pciconfig.pio = bus.default + bus.responder_set = True + bus.responder = self.pciconfig self.fake_sm_chip.pio = bus.port self.fake_uart1.pio = bus.port self.fake_uart2.pio = bus.port |