diff options
Diffstat (limited to 'src/python/m5/objects')
-rw-r--r-- | src/python/m5/objects/Bus.py | 4 | ||||
-rw-r--r-- | src/python/m5/objects/Device.py | 16 | ||||
-rw-r--r-- | src/python/m5/objects/PhysicalMemory.py | 1 | ||||
-rw-r--r-- | src/python/m5/objects/System.py | 25 | ||||
-rw-r--r-- | src/python/m5/objects/T1000.py | 82 | ||||
-rw-r--r-- | src/python/m5/objects/Tsunami.py | 11 |
6 files changed, 126 insertions, 13 deletions
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index e7019f3ac..8226fe8d2 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -2,7 +2,7 @@ from m5 import build_env from m5.params import * from m5.proxy import * from MemObject import MemObject -from Tsunami import BadAddr +from Device import BadAddr class Bus(MemObject): type = 'Bus' @@ -12,7 +12,7 @@ class Bus(MemObject): width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") if build_env['FULL_SYSTEM']: - default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") responder = BadAddr(pio_addr=0x0, pio_latency="1ps") + default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") else: default = Port("Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index 4672d1065..f4b873a60 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,3 +19,19 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + +class IsaFake(BasicPioDevice): + type = 'IsaFake' + pio_size = Param.Addr(0x8, "Size of address range") + ret_data8 = Param.UInt8(0xFF, "Default data to return") + ret_data16 = Param.UInt16(0xFFFF, "Default data to return") + ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") + ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") + ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") + update_data = Param.Bool(False, "Update the data that is returned on writes") + warn_access = Param.String("", "String to print when device is accessed") + +class BadAddr(IsaFake): + ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") + + diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py index 4e097543d..b8df6229e 100644 --- a/src/python/m5/objects/PhysicalMemory.py +++ b/src/python/m5/objects/PhysicalMemory.py @@ -9,6 +9,7 @@ class PhysicalMemory(MemObject): range = Param.AddrRange(AddrRange('128MB'), "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency(Parent.clock, "latency of an access") + zero = Param.Bool(False, "zero initialize memory") class DRAMMemory(PhysicalMemory): type = 'DRAMMemory' diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py index 908c3d4ad..810a320be 100644 --- a/src/python/m5/objects/System.py +++ b/src/python/m5/objects/System.py @@ -15,7 +15,7 @@ class System(SimObject): "boot processor frequency") init_param = Param.UInt64(0, "numerical value to pass into simulator") boot_osflags = Param.String("a", "boot flags to pass to the kernel") - kernel = Param.String("file that contains the kernel code") + kernel = Param.String("", "file that contains the kernel code") readfile = Param.String("", "file to read startup script from") symbolfile = Param.String("", "file to get the symbols from") @@ -29,17 +29,40 @@ class AlphaSystem(System): class SparcSystem(System): type = 'SparcSystem' _rom_base = 0xfff0000000 + _nvram_base = 0x1f11000000 + _hypervisor_desc_base = 0x1f12080000 + _partition_desc_base = 0x1f12000000 # ROM for OBP/Reset/Hypervisor rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')), "Memory to hold the ROM data") + # nvram + nvram = Param.PhysicalMemory( + PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')), + "Memory to hold the nvram data") + # hypervisor description + hypervisor_desc = Param.PhysicalMemory( + PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')), + "Memory to hold the hypervisor description") + # partition description + partition_desc = Param.PhysicalMemory( + PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')), + "Memory to hold the partition description") reset_addr = Param.Addr(_rom_base, "Address to load ROM at") hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base, "Address to load hypervisor at") openboot_addr = Param.Addr(Addr('512kB') + _rom_base, "Address to load openboot at") + nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram") + hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base, + "Address for the hypervisor description") + partition_desc_addr = Param.Addr(_partition_desc_base, + "Address for the partition description") reset_bin = Param.String("file that contains the reset code") hypervisor_bin = Param.String("file that contains the hypervisor code") openboot_bin = Param.String("file that contains the openboot code") + nvram_bin = Param.String("file that contains the contents of nvram") + hypervisor_desc_bin = Param.String("file that contains the hypervisor description") + partition_desc_bin = Param.String("file that contains the partition description") diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py new file mode 100644 index 000000000..79195d976 --- /dev/null +++ b/src/python/m5/objects/T1000.py @@ -0,0 +1,82 @@ +from m5.params import * +from m5.proxy import * +from Device import BasicPioDevice, IsaFake, BadAddr +from Uart import Uart8250 +from Platform import Platform +from SimConsole import SimConsole, ConsoleListener + +class T1000(Platform): + type = 'T1000' + system = Param.System(Parent.any, "system") + + fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000, + warn_access="Accessing Clock Unit -- Unimplemented!") + + fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, + ret_data64=0x0000000000000000, update_data=False, + warn_access="Accessing Memory Banks -- Unimplemented!") + + fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000, + warn_access="Accessing IOB -- Unimplemented!") + + fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000, + warn_access="Accessing JBI -- Unimplemented!") + + fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, + ret_data64=0x0000000000000001, update_data=True, + warn_access="Accessing L2 Cache Banks -- Unimplemented!") + + fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, + ret_data64=0x0000000000000000, update_data=True, + warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") + + fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000, + warn_access="Accessing SSI -- Unimplemented!") + + hvuart = Uart8250(pio_addr=0xfff0c2c000) + puart0 = Uart8250(pio_addr=0x1f10000000) + console = SimConsole(listener = ConsoleListener()) + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIO(self, bus): + self.fake_clk.pio = bus.port + self.fake_membnks.pio = bus.port + self.fake_iob.pio = bus.port + self.fake_jbi.pio = bus.port + self.fake_l2_1.pio = bus.port + self.fake_l2_2.pio = bus.port + self.fake_l2_3.pio = bus.port + self.fake_l2_4.pio = bus.port + self.fake_l2esr_1.pio = bus.port + self.fake_l2esr_2.pio = bus.port + self.fake_l2esr_3.pio = bus.port + self.fake_l2esr_4.pio = bus.port + self.fake_ssi.pio = bus.port + self.puart0.pio = bus.port + self.hvuart.pio = bus.port diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index ffe93727b..c18210bba 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -1,6 +1,6 @@ from m5.params import * from m5.proxy import * -from Device import BasicPioDevice +from Device import BasicPioDevice, IsaFake, BadAddr from Platform import Platform from AlphaConsole import AlphaConsole from Uart import Uart8250 @@ -11,15 +11,6 @@ class TsunamiCChip(BasicPioDevice): type = 'TsunamiCChip' tsunami = Param.Tsunami(Parent.any, "Tsunami") -class IsaFake(BasicPioDevice): - type = 'IsaFake' - pio_size = Param.Addr(0x8, "Size of address range") - ret_data = Param.UInt8(0xFF, "Default data to return") - ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") - -class BadAddr(IsaFake): - ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") - class TsunamiIO(BasicPioDevice): type = 'TsunamiIO' time = Param.UInt64(1136073600, |