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-rw-r--r--src/python/m5/objects/BaseCPU.py4
-rw-r--r--src/python/m5/objects/PhysicalMemory.py2
-rw-r--r--src/python/m5/objects/Root.py7
3 files changed, 4 insertions, 9 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 67a28a61e..986220c3f 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,8 +47,8 @@ class BaseCPU(SimObject):
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
- clock = Param.Clock(Parent.clock, "clock speed")
- phase = Param.Latency("0ns", "clock phase")
+ clock = Param.Clock('1t', "clock speed")
+ phase = Param.Latency('0ns', "clock phase")
_mem_ports = []
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index b8df6229e..c389e4a7f 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -8,7 +8,7 @@ class PhysicalMemory(MemObject):
functional = Port("Functional Access Port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
- latency = Param.Latency(Parent.clock, "latency of an access")
+ latency = Param.Latency('1t', "latency of an access")
zero = Param.Bool(False, "zero initialize memory")
class DRAMMemory(PhysicalMemory):
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 8db4fa5a2..2b0e736e7 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -3,9 +3,4 @@ from m5.params import *
class Root(SimObject):
type = 'Root'
- clock = Param.RootClock('1THz', "tick frequency")
- max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
- progress_interval = Param.Tick('0',
- "print a progress message every n ticks (0 = never)")
- output_file = Param.String('cout', "file to dump simulator output to")
- checkpoint = Param.String('', "checkpoint file to load")
+ dummy = Param.Int(0, "We don't support objects without params")