summaryrefslogtreecommitdiff
path: root/src/python/m5
diff options
context:
space:
mode:
Diffstat (limited to 'src/python/m5')
-rw-r--r--src/python/m5/__init__.py30
-rw-r--r--src/python/m5/config.py6
-rw-r--r--src/python/m5/objects/Bus.py1
-rw-r--r--src/python/m5/objects/O3CPU.py8
-rw-r--r--src/python/m5/objects/Pci.py10
5 files changed, 29 insertions, 26 deletions
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index 828165d15..579785a46 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -213,14 +213,14 @@ atexit.register(cc_main.doExitCleanup)
# matter since most scripts will probably 'from m5.objects import *'.
import objects
-def doQuiesce(root):
- quiesce = cc_main.createCountedQuiesce()
- unready_objects = root.startQuiesce(quiesce, True)
- # If we've got some objects that can't quiesce immediately, then simulate
+def doDrain(root):
+ drain_event = cc_main.createCountedDrain()
+ unready_objects = root.startDrain(drain_event, True)
+ # If we've got some objects that can't drain immediately, then simulate
if unready_objects > 0:
- quiesce.setCount(unready_objects)
+ drain_event.setCount(unready_objects)
simulate()
- cc_main.cleanupCountedQuiesce(quiesce)
+ cc_main.cleanupCountedDrain(drain_event)
def resume(root):
root.resume()
@@ -228,7 +228,7 @@ def resume(root):
def checkpoint(root):
if not isinstance(root, objects.Root):
raise TypeError, "Object is not a root object. Checkpoint must be called on a root object."
- doQuiesce(root)
+ doDrain(root)
print "Writing checkpoint"
cc_main.serializeAll()
resume(root)
@@ -241,7 +241,7 @@ def changeToAtomic(system):
if not isinstance(system, objects.Root) and not isinstance(system, System):
raise TypeError, "Object is not a root or system object. Checkpoint must be "
"called on a root object."
- doQuiesce(system)
+ doDrain(system)
print "Changing memory mode to atomic"
system.changeTiming(cc_main.SimObject.Atomic)
resume(system)
@@ -250,7 +250,7 @@ def changeToTiming(system):
if not isinstance(system, objects.Root) and not isinstance(system, System):
raise TypeError, "Object is not a root or system object. Checkpoint must be "
"called on a root object."
- doQuiesce(system)
+ doDrain(system)
print "Changing memory mode to timing"
system.changeTiming(cc_main.SimObject.Timing)
resume(system)
@@ -271,16 +271,16 @@ def switchCpus(cpuList):
if not isinstance(cpu, objects.BaseCPU):
raise TypeError, "%s is not of type BaseCPU", cpu
- # Quiesce all of the individual CPUs
- quiesce = cc_main.createCountedQuiesce()
+ # Drain all of the individual CPUs
+ drain_event = cc_main.createCountedDrain()
unready_cpus = 0
for old_cpu in old_cpus:
- unready_cpus += old_cpu.startQuiesce(quiesce, False)
- # If we've got some objects that can't quiesce immediately, then simulate
+ unready_cpus += old_cpu.startDrain(drain_event, False)
+ # If we've got some objects that can't drain immediately, then simulate
if unready_cpus > 0:
- quiesce.setCount(unready_cpus)
+ drain_event.setCount(unready_cpus)
simulate()
- cc_main.cleanupCountedQuiesce(quiesce)
+ cc_main.cleanupCountedDrain(drain_event)
# Now all of the CPUs are ready to be switched out
for old_cpu in old_cpus:
old_cpu._ccObject.switchOut()
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index 6f2873d40..8291e1e1b 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -543,15 +543,15 @@ class SimObject(object):
for child in self._children.itervalues():
child.connectPorts()
- def startQuiesce(self, quiesce_event, recursive):
+ def startDrain(self, drain_event, recursive):
count = 0
# ParamContexts don't serialize
if isinstance(self, SimObject) and not isinstance(self, ParamContext):
- if self._ccObject.quiesce(quiesce_event):
+ if not self._ccObject.drain(drain_event):
count = 1
if recursive:
for child in self._children.itervalues():
- count += child.startQuiesce(quiesce_event, True)
+ count += child.startDrain(drain_event, True)
return count
def resume(self):
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 019e15034..e0278e6c3 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -4,4 +4,5 @@ from MemObject import MemObject
class Bus(MemObject):
type = 'Bus'
port = VectorPort("vector port for connecting devices")
+ default = Port("Default port for requests that aren't handeled by a device.")
bus_id = Param.Int(0, "blah")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 4ecfa8fbd..9ccbdcf53 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -37,12 +37,10 @@ class DerivO3CPU(BaseCPU):
"Issue/Execute/Writeback delay")
issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
"to the IEW stage)")
+ dispatchWidth = Param.Unsigned("Dispatch width")
issueWidth = Param.Unsigned("Issue width")
- executeWidth = Param.Unsigned("Execute width")
- executeIntWidth = Param.Unsigned("Integer execute width")
- executeFloatWidth = Param.Unsigned("Floating point execute width")
- executeBranchWidth = Param.Unsigned("Branch execute width")
- executeMemoryWidth = Param.Unsigned("Memory execute width")
+ wbWidth = Param.Unsigned("Writeback width")
+ wbDepth = Param.Unsigned("Writeback depth")
fuPool = Param.FUPool(NULL, "Functional Unit pool")
iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
index 9e1e91b13..29014bb37 100644
--- a/src/python/m5/objects/Pci.py
+++ b/src/python/m5/objects/Pci.py
@@ -1,5 +1,5 @@
from m5.config import *
-from Device import BasicPioDevice, DmaDevice
+from Device import BasicPioDevice, DmaDevice, PioDevice
class PciConfigData(SimObject):
type = 'PciConfigData'
@@ -38,18 +38,22 @@ class PciConfigData(SimObject):
MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-class PciConfigAll(BasicPioDevice):
+class PciConfigAll(PioDevice):
type = 'PciConfigAll'
+ pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
+ bus = Param.UInt8(0x00, "PCI bus to act as config space for")
+ size = Param.MemorySize32('16MB', "Size of config space")
+
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
+ config = Port("PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
configdata = Param.PciConfigData(Parent.any, "PCI Config data")
- configspace = Param.PciConfigAll(Parent.any, "PCI Configspace")
class PciFake(PciDevice):
type = 'PciFake'
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-10 19:40:46 +0000