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-rw-r--r--src/python/m5/objects/AlphaConsole.py10
-rw-r--r--src/python/m5/objects/AlphaTLB.py14
-rw-r--r--src/python/m5/objects/BadDevice.py6
-rw-r--r--src/python/m5/objects/BaseCPU.py73
-rw-r--r--src/python/m5/objects/BaseCache.py63
-rw-r--r--src/python/m5/objects/Bridge.py16
-rw-r--r--src/python/m5/objects/Bus.py19
-rw-r--r--src/python/m5/objects/CoherenceProtocol.py8
-rw-r--r--src/python/m5/objects/Device.py43
-rw-r--r--src/python/m5/objects/DiskImage.py16
-rw-r--r--src/python/m5/objects/Ethernet.py200
-rw-r--r--src/python/m5/objects/FUPool.py12
-rw-r--r--src/python/m5/objects/FuncUnit.py18
-rw-r--r--src/python/m5/objects/FuncUnitConfig.py41
-rw-r--r--src/python/m5/objects/Ide.py40
-rw-r--r--src/python/m5/objects/IntrControl.py6
-rw-r--r--src/python/m5/objects/MemObject.py6
-rw-r--r--src/python/m5/objects/MemTest.py24
-rw-r--r--src/python/m5/objects/O3CPU.py123
-rw-r--r--src/python/m5/objects/OzoneCPU.py95
-rw-r--r--src/python/m5/objects/Pci.py59
-rw-r--r--src/python/m5/objects/PhysicalMemory.py29
-rw-r--r--src/python/m5/objects/Platform.py7
-rw-r--r--src/python/m5/objects/Process.py36
-rw-r--r--src/python/m5/objects/Repl.py11
-rw-r--r--src/python/m5/objects/Root.py6
-rw-r--r--src/python/m5/objects/SimConsole.py11
-rw-r--r--src/python/m5/objects/SimpleDisk.py7
-rw-r--r--src/python/m5/objects/SimpleOzoneCPU.py87
-rw-r--r--src/python/m5/objects/SparcTLB.py14
-rw-r--r--src/python/m5/objects/System.py68
-rw-r--r--src/python/m5/objects/T1000.py106
-rw-r--r--src/python/m5/objects/Tsunami.py95
-rw-r--r--src/python/m5/objects/Uart.py17
34 files changed, 0 insertions, 1386 deletions
diff --git a/src/python/m5/objects/AlphaConsole.py b/src/python/m5/objects/AlphaConsole.py
deleted file mode 100644
index f968aaa40..000000000
--- a/src/python/m5/objects/AlphaConsole.py
+++ /dev/null
@@ -1,10 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice
-
-class AlphaConsole(BasicPioDevice):
- type = 'AlphaConsole'
- cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
- disk = Param.SimpleDisk("Simple Disk")
- sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
- system = Param.AlphaSystem(Parent.any, "system object")
diff --git a/src/python/m5/objects/AlphaTLB.py b/src/python/m5/objects/AlphaTLB.py
deleted file mode 100644
index af7c04a84..000000000
--- a/src/python/m5/objects/AlphaTLB.py
+++ /dev/null
@@ -1,14 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class AlphaTLB(SimObject):
- type = 'AlphaTLB'
- abstract = True
- size = Param.Int("TLB size")
-
-class AlphaDTB(AlphaTLB):
- type = 'AlphaDTB'
- size = 64
-
-class AlphaITB(AlphaTLB):
- type = 'AlphaITB'
- size = 48
diff --git a/src/python/m5/objects/BadDevice.py b/src/python/m5/objects/BadDevice.py
deleted file mode 100644
index 919623887..000000000
--- a/src/python/m5/objects/BadDevice.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.params import *
-from Device import BasicPioDevice
-
-class BadDevice(BasicPioDevice):
- type = 'BadDevice'
- devicename = Param.String("Name of device to error on")
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
deleted file mode 100644
index 986220c3f..000000000
--- a/src/python/m5/objects/BaseCPU.py
+++ /dev/null
@@ -1,73 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from AlphaTLB import AlphaDTB, AlphaITB
-from SparcTLB import SparcDTB, SparcITB
-from Bus import Bus
-import sys
-
-class BaseCPU(SimObject):
- type = 'BaseCPU'
- abstract = True
-
- system = Param.System(Parent.any, "system object")
- cpu_id = Param.Int("CPU identifier")
-
- if build_env['FULL_SYSTEM']:
- do_quiesce = Param.Bool(True, "enable quiesce instructions")
- do_checkpoint_insts = Param.Bool(True,
- "enable checkpoint pseudo instructions")
- do_statistics_insts = Param.Bool(True,
- "enable statistics pseudo instructions")
-
- if build_env['TARGET_ISA'] == 'sparc':
- dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
- itb = Param.SparcITB(SparcITB(), "Instruction TLB")
- elif build_env['TARGET_ISA'] == 'alpha':
- dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
- itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
- else:
- print "Unknown architecture, can't pick TLBs"
- sys.exit(1)
- else:
- workload = VectorParam.Process("processes to run")
-
- max_insts_all_threads = Param.Counter(0,
- "terminate when all threads have reached this inst count")
- max_insts_any_thread = Param.Counter(0,
- "terminate when any thread reaches this inst count")
- max_loads_all_threads = Param.Counter(0,
- "terminate when all threads have reached this load count")
- max_loads_any_thread = Param.Counter(0,
- "terminate when any thread reaches this load count")
- progress_interval = Param.Tick(0,
- "interval to print out the progress message")
-
- defer_registration = Param.Bool(False,
- "defer registration with system (for sampling)")
-
- clock = Param.Clock('1t', "clock speed")
- phase = Param.Latency('0ns', "clock phase")
-
- _mem_ports = []
-
- def connectMemPorts(self, bus):
- for p in self._mem_ports:
- exec('self.%s = bus.port' % p)
-
- def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) == 2)
- self.icache = ic
- self.dcache = dc
- self.icache_port = ic.cpu_side
- self.dcache_port = dc.cpu_side
- self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-
- def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
- self.addPrivateSplitL1Caches(ic, dc)
- self.toL2Bus = Bus()
- self.connectMemPorts(self.toL2Bus)
- self.l2cache = l2c
- self.l2cache.cpu_side = self.toL2Bus.port
- self._mem_ports = ['l2cache.mem_side']
diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py
deleted file mode 100644
index 7df5215e4..000000000
--- a/src/python/m5/objects/BaseCache.py
+++ /dev/null
@@ -1,63 +0,0 @@
-from m5.params import *
-from MemObject import MemObject
-
-class Prefetch(Enum): vals = ['none', 'tagged', 'stride', 'ghb']
-
-class BaseCache(MemObject):
- type = 'BaseCache'
- adaptive_compression = Param.Bool(False,
- "Use an adaptive compression scheme")
- assoc = Param.Int("associativity")
- block_size = Param.Int("block size in bytes")
- latency = Param.Latency("Latency")
- compressed_bus = Param.Bool(False,
- "This cache connects to a compressed memory")
- compression_latency = Param.Latency('0ns',
- "Latency in cycles of compression algorithm")
- hash_delay = Param.Int(1, "time in cycles of hash access")
- lifo = Param.Bool(False,
- "whether this NIC partition should use LIFO repl. policy")
- max_miss_count = Param.Counter(0,
- "number of misses to handle before calling exit")
- mshrs = Param.Int("number of MSHRs (max outstanding requests)")
- prioritizeRequests = Param.Bool(False,
- "always service demand misses first")
- protocol = Param.CoherenceProtocol(NULL, "coherence protocol to use")
- repl = Param.Repl(NULL, "replacement policy")
- size = Param.MemorySize("capacity in bytes")
- split = Param.Bool(False, "whether or not this cache is split")
- split_size = Param.Int(0,
- "How many ways of the cache belong to CPU/LRU partition")
- store_compressed = Param.Bool(False,
- "Store compressed data in the cache")
- subblock_size = Param.Int(0,
- "Size of subblock in IIC used for compression")
- tgts_per_mshr = Param.Int("max number of accesses per MSHR")
- trace_addr = Param.Addr(0, "address to trace")
- two_queue = Param.Bool(False,
- "whether the lifo should have two queue replacement")
- write_buffers = Param.Int(8, "number of write buffers")
- prefetch_miss = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Miss stream")
- prefetch_access = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Access stream")
- prefetcher_size = Param.Int(100,
- "Number of entries in the harware prefetch queue")
- prefetch_past_page = Param.Bool(False,
- "Allow prefetches to cross virtual page boundaries")
- prefetch_serial_squash = Param.Bool(False,
- "Squash prefetches with a later time on a subsequent miss")
- prefetch_degree = Param.Int(1,
- "Degree of the prefetch depth")
- prefetch_latency = Param.Tick(10,
- "Latency of the prefetcher")
- prefetch_policy = Param.Prefetch('none',
- "Type of prefetcher to use")
- prefetch_cache_check_push = Param.Bool(True,
- "Check if in cash on push or pop of prefetch queue")
- prefetch_use_cpu_id = Param.Bool(True,
- "Use the CPU ID to seperate calculations of prefetches")
- prefetch_data_accesses_only = Param.Bool(False,
- "Only prefetch on data not on instruction accesses")
- cpu_side = Port("Port on side closer to CPU")
- mem_side = Port("Port on side closer to MEM")
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
deleted file mode 100644
index 33b24ad3c..000000000
--- a/src/python/m5/objects/Bridge.py
+++ /dev/null
@@ -1,16 +0,0 @@
-from m5.params import *
-from MemObject import MemObject
-
-class Bridge(MemObject):
- type = 'Bridge'
- side_a = Port('Side A port')
- side_b = Port('Side B port')
- req_size_a = Param.Int(16, "The number of requests to buffer")
- req_size_b = Param.Int(16, "The number of requests to buffer")
- resp_size_a = Param.Int(16, "The number of requests to buffer")
- resp_size_b = Param.Int(16, "The number of requests to buffer")
- delay = Param.Latency('0ns', "The latency of this bridge")
- nack_delay = Param.Latency('0ns', "The latency of this bridge")
- write_ack = Param.Bool(False, "Should this bridge ack writes")
- fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
- fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
deleted file mode 100644
index 48dbbe307..000000000
--- a/src/python/m5/objects/Bus.py
+++ /dev/null
@@ -1,19 +0,0 @@
-from m5 import build_env
-from m5.params import *
-from m5.proxy import *
-from MemObject import MemObject
-from Device import BadAddr
-
-class Bus(MemObject):
- type = 'Bus'
- port = VectorPort("vector port for connecting devices")
- bus_id = Param.Int(0, "blah")
- clock = Param.Clock("1GHz", "bus clock speed")
- width = Param.Int(64, "bus width (bytes)")
- responder_set = Param.Bool(False, "Did the user specify a default responder.")
- block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
- if build_env['FULL_SYSTEM']:
- responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
- default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
- else:
- default = Port("Default port for requests that aren't handled by a device.")
diff --git a/src/python/m5/objects/CoherenceProtocol.py b/src/python/m5/objects/CoherenceProtocol.py
deleted file mode 100644
index 82adb6862..000000000
--- a/src/python/m5/objects/CoherenceProtocol.py
+++ /dev/null
@@ -1,8 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class Coherence(Enum): vals = ['uni', 'msi', 'mesi', 'mosi', 'moesi']
-
-class CoherenceProtocol(SimObject):
- type = 'CoherenceProtocol'
- do_upgrades = Param.Bool(True, "use upgrade transactions?")
- protocol = Param.Coherence("name of coherence protocol")
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
deleted file mode 100644
index 90fbfb552..000000000
--- a/src/python/m5/objects/Device.py
+++ /dev/null
@@ -1,43 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from MemObject import MemObject
-
-class PioDevice(MemObject):
- type = 'PioDevice'
- abstract = True
- pio = Port("Programmed I/O port")
- platform = Param.Platform(Parent.any, "Platform this device is part of")
- system = Param.System(Parent.any, "System this device is part of")
-
-class BasicPioDevice(PioDevice):
- type = 'BasicPioDevice'
- abstract = True
- pio_addr = Param.Addr("Device Address")
- pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
-
-class DmaDevice(PioDevice):
- type = 'DmaDevice'
- abstract = True
- dma = Port(Self.pio.peerObj.port, "DMA port")
- min_backoff_delay = Param.Latency('4ns',
- "min time between a nack packet being received and the next request made by the device")
- max_backoff_delay = Param.Latency('10us',
- "max time between a nack packet being received and the next request made by the device")
-
-
-
-class IsaFake(BasicPioDevice):
- type = 'IsaFake'
- pio_size = Param.Addr(0x8, "Size of address range")
- ret_data8 = Param.UInt8(0xFF, "Default data to return")
- ret_data16 = Param.UInt16(0xFFFF, "Default data to return")
- ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return")
- ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return")
- ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access")
- update_data = Param.Bool(False, "Update the data that is returned on writes")
- warn_access = Param.String("", "String to print when device is accessed")
-
-class BadAddr(IsaFake):
- ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access")
-
-
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
deleted file mode 100644
index d0ada7ee1..000000000
--- a/src/python/m5/objects/DiskImage.py
+++ /dev/null
@@ -1,16 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class DiskImage(SimObject):
- type = 'DiskImage'
- abstract = True
- image_file = Param.String("disk image file")
- read_only = Param.Bool(False, "read only image")
-
-class RawDiskImage(DiskImage):
- type = 'RawDiskImage'
-
-class CowDiskImage(DiskImage):
- type = 'CowDiskImage'
- child = Param.DiskImage(RawDiskImage(read_only=True),
- "child image")
- table_size = Param.Int(65536, "initial table size")
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
deleted file mode 100644
index bfe30950c..000000000
--- a/src/python/m5/objects/Ethernet.py
+++ /dev/null
@@ -1,200 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from Device import DmaDevice
-from Pci import PciDevice, PciConfigData
-
-class EtherInt(SimObject):
- type = 'EtherInt'
- abstract = True
- peer = Param.EtherInt(NULL, "peer interface")
-
-class EtherLink(SimObject):
- type = 'EtherLink'
- int1 = Param.EtherInt("interface 1")
- int2 = Param.EtherInt("interface 2")
- delay = Param.Latency('0us', "packet transmit delay")
- delay_var = Param.Latency('0ns', "packet transmit delay variability")
- speed = Param.NetworkBandwidth('1Gbps', "link speed")
- dump = Param.EtherDump(NULL, "dump object")
-
-class EtherBus(SimObject):
- type = 'EtherBus'
- loopback = Param.Bool(True, "send packet back to the sending interface")
- dump = Param.EtherDump(NULL, "dump object")
- speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second")
-
-class EtherTap(EtherInt):
- type = 'EtherTap'
- bufsz = Param.Int(10000, "tap buffer size")
- dump = Param.EtherDump(NULL, "dump object")
- port = Param.UInt16(3500, "tap port")
-
-class EtherDump(SimObject):
- type = 'EtherDump'
- file = Param.String("dump file")
- maxlen = Param.Int(96, "max portion of packet data to dump")
-
-if build_env['ALPHA_TLASER']:
-
- class EtherDev(DmaDevice):
- type = 'EtherDev'
- hardware_address = Param.EthernetAddr(NextEthernetAddr,
- "Ethernet Hardware Address")
-
- dma_data_free = Param.Bool(False, "DMA of Data is free")
- dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
- dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
- dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
- dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
- dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
- rx_filter = Param.Bool(True, "Enable Receive Filter")
- rx_delay = Param.Latency('1us', "Receive Delay")
- tx_delay = Param.Latency('1us', "Transmit Delay")
-
- intr_delay = Param.Latency('0us', "Interrupt Delay")
- payload_bus = Param.Bus(NULL, "The IO Bus to attach to for payload")
- physmem = Param.PhysicalMemory(Parent.any, "Physical Memory")
- tlaser = Param.Turbolaser(Parent.any, "Turbolaser")
-
- class EtherDevInt(EtherInt):
- type = 'EtherDevInt'
- device = Param.EtherDev("Ethernet device of this interface")
-
-
-class IGbE(PciDevice):
- type = 'IGbE'
- hardware_address = Param.String("Ethernet Hardware Address")
- use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)")
- rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO")
- tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO")
- rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
- tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache")
- clock = Param.Clock('500MHz', "Clock speed of the device")
-
-
-class IGbEPciData(PciConfigData):
- VendorID = 0x8086
- DeviceID = 0x1075
- SubsystemID = 0x1008
- SubsystemVendorID = 0x8086
- Status = 0x0000
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000000
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x00
- MinimumGrant = 0xff
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '128kB'
-
-class IGbEInt(EtherInt):
- type = 'IGbEInt'
- device = Param.IGbE("Ethernet device of this interface")
-
-
-
-class EtherDevBase(PciDevice):
- hardware_address = Param.EthernetAddr(NextEthernetAddr,
- "Ethernet Hardware Address")
-
- clock = Param.Clock('0ns', "State machine processor frequency")
-
- dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
- dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
- dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
- dma_write_factor = Param.Latency('0us', "multiplier for dma writes")
-
- rx_delay = Param.Latency('1us', "Receive Delay")
- tx_delay = Param.Latency('1us', "Transmit Delay")
- rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo")
- tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo")
-
- rx_filter = Param.Bool(True, "Enable Receive Filter")
- intr_delay = Param.Latency('10us', "Interrupt propagation delay")
- rx_thread = Param.Bool(False, "dedicated kernel thread for transmit")
- tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
- rss = Param.Bool(False, "Receive Side Scaling")
-
-class NSGigEPciData(PciConfigData):
- VendorID = 0x100B
- DeviceID = 0x0022
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000001
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '256B'
- BAR1Size = '4kB'
-
-class NSGigE(EtherDevBase):
- type = 'NSGigE'
-
- dma_data_free = Param.Bool(False, "DMA of Data is free")
- dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
- dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
-
- configdata = NSGigEPciData()
-
-
-class NSGigEInt(EtherInt):
- type = 'NSGigEInt'
- device = Param.NSGigE("Ethernet device of this interface")
-
-class SinicPciData(PciConfigData):
- VendorID = 0x1291
- DeviceID = 0x1293
- Status = 0x0290
- SubClassCode = 0x00
- ClassCode = 0x02
- ProgIF = 0x00
- BAR0 = 0x00000000
- BAR1 = 0x00000000
- BAR2 = 0x00000000
- BAR3 = 0x00000000
- BAR4 = 0x00000000
- BAR5 = 0x00000000
- MaximumLatency = 0x34
- MinimumGrant = 0xb0
- InterruptLine = 0x1e
- InterruptPin = 0x01
- BAR0Size = '64kB'
-
-class Sinic(EtherDevBase):
- type = 'Sinic'
-
- rx_max_copy = Param.MemorySize('1514B', "rx max copy")
- tx_max_copy = Param.MemorySize('16kB', "tx max copy")
- rx_max_intr = Param.UInt32(10, "max rx packets per interrupt")
- rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold")
- rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold")
- tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold")
- tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold")
- virtual_count = Param.UInt32(1, "Virtualized SINIC")
- zero_copy = Param.Bool(False, "Zero copy receive")
- delay_copy = Param.Bool(False, "Delayed copy transmit")
- virtual_addr = Param.Bool(False, "Virtual addressing")
-
- configdata = SinicPciData()
-
-class SinicInt(EtherInt):
- type = 'SinicInt'
- device = Param.Sinic("Ethernet device of this interface")
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
deleted file mode 100644
index 916183bd7..000000000
--- a/src/python/m5/objects/FUPool.py
+++ /dev/null
@@ -1,12 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
-
-class FUPool(SimObject):
- type = 'FUPool'
- FUList = VectorParam.FUDesc("list of FU's for this pool")
-
-class DefaultFUPool(FUPool):
- FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
- WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py
deleted file mode 100644
index f0ad55f7a..000000000
--- a/src/python/m5/objects/FuncUnit.py
+++ /dev/null
@@ -1,18 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-
-class OpType(Enum):
- vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd',
- 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt',
- 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch']
-
-class OpDesc(SimObject):
- type = 'OpDesc'
- issueLat = Param.Int(1, "cycles until another can be issued")
- opClass = Param.OpType("type of operation")
- opLat = Param.Int(1, "cycles until result is available")
-
-class FUDesc(SimObject):
- type = 'FUDesc'
- count = Param.Int("number of these FU's available")
- opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
deleted file mode 100644
index 43d7a4bb7..000000000
--- a/src/python/m5/objects/FuncUnitConfig.py
+++ /dev/null
@@ -1,41 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from FuncUnit import *
-
-class IntALU(FUDesc):
- opList = [ OpDesc(opClass='IntAlu') ]
- count = 6
-
-class IntMultDiv(FUDesc):
- opList = [ OpDesc(opClass='IntMult', opLat=3),
- OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
- count=2
-
-class FP_ALU(FUDesc):
- opList = [ OpDesc(opClass='FloatAdd', opLat=2),
- OpDesc(opClass='FloatCmp', opLat=2),
- OpDesc(opClass='FloatCvt', opLat=2) ]
- count = 4
-
-class FP_MultDiv(FUDesc):
- opList = [ OpDesc(opClass='FloatMult', opLat=4),
- OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
- OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
- count = 2
-
-class ReadPort(FUDesc):
- opList = [ OpDesc(opClass='MemRead') ]
- count = 0
-
-class WritePort(FUDesc):
- opList = [ OpDesc(opClass='MemWrite') ]
- count = 0
-
-class RdWrPort(FUDesc):
- opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
- count = 4
-
-class IprPort(FUDesc):
- opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
- count = 1
-
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
deleted file mode 100644
index ef7e28785..000000000
--- a/src/python/m5/objects/Ide.py
+++ /dev/null
@@ -1,40 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from Pci import PciDevice, PciConfigData
-
-class IdeID(Enum): vals = ['master', 'slave']
-
-class IdeControllerPciData(PciConfigData):
- VendorID = 0x8086
- DeviceID = 0x7111
- Command = 0x0
- Status = 0x280
- Revision = 0x0
- ClassCode = 0x01
- SubClassCode = 0x01
- ProgIF = 0x85
- BAR0 = 0x00000001
- BAR1 = 0x00000001
- BAR2 = 0x00000001
- BAR3 = 0x00000001
- BAR4 = 0x00000001
- BAR5 = 0x00000001
- InterruptLine = 0x1f
- InterruptPin = 0x01
- BAR0Size = '8B'
- BAR1Size = '4B'
- BAR2Size = '8B'
- BAR3Size = '4B'
- BAR4Size = '16B'
-
-class IdeDisk(SimObject):
- type = 'IdeDisk'
- delay = Param.Latency('1us', "Fixed disk delay in microseconds")
- driveID = Param.IdeID('master', "Drive ID")
- image = Param.DiskImage("Disk image")
-
-class IdeController(PciDevice):
- type = 'IdeController'
- disks = VectorParam.IdeDisk("IDE disks attached to this controller")
-
- configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
deleted file mode 100644
index 398ba47f9..000000000
--- a/src/python/m5/objects/IntrControl.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class IntrControl(SimObject):
- type = 'IntrControl'
- sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/python/m5/objects/MemObject.py b/src/python/m5/objects/MemObject.py
deleted file mode 100644
index 8982d553d..000000000
--- a/src/python/m5/objects/MemObject.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.SimObject import SimObject
-
-class MemObject(SimObject):
- type = 'MemObject'
- abstract = True
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
deleted file mode 100644
index 1219ddd4d..000000000
--- a/src/python/m5/objects/MemTest.py
+++ /dev/null
@@ -1,24 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-
-class MemTest(SimObject):
- type = 'MemTest'
- max_loads = Param.Counter("number of loads to execute")
- atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
- memory_size = Param.Int(65536, "memory size")
- percent_dest_unaligned = Param.Percent(50,
- "percent of copy dest address that are unaligned")
- percent_reads = Param.Percent(65, "target read percentage")
- percent_source_unaligned = Param.Percent(50,
- "percent of copy source address that are unaligned")
- percent_functional = Param.Percent(50, "percent of access that are functional")
- percent_uncacheable = Param.Percent(10,
- "target uncacheable percentage")
- progress_interval = Param.Counter(1000000,
- "progress report interval (in accesses)")
- trace_addr = Param.Addr(0, "address to trace")
-
- test = Port("Port to the memory system to test")
- functional = Port("Port to the functional memory used for verification")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
deleted file mode 100644
index 5fba4e96f..000000000
--- a/src/python/m5/objects/O3CPU.py
+++ /dev/null
@@ -1,123 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from BaseCPU import BaseCPU
-from Checker import O3Checker
-from FUPool import *
-
-class DerivO3CPU(BaseCPU):
- type = 'DerivO3CPU'
- activity = Param.Unsigned(0, "Initial count")
- numThreads = Param.Unsigned(1, "number of HW thread contexts")
-
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
- if build_env['USE_CHECKER']:
- if not build_env['FULL_SYSTEM']:
- checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
- exitOnError=False,
- updateOnError=True,
- warnOnlyOnLoadError=False),
- "checker")
- else:
- checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
- warnOnlyOnLoadError=False), "checker")
- checker.itb = Parent.itb
- checker.dtb = Parent.dtb
-
- cachePorts = Param.Unsigned("Cache Ports")
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
- _mem_ports = ['icache_port', 'dcache_port']
-
- decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
- renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
- iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch "
- "delay")
- commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay")
- fetchWidth = Param.Unsigned(8, "Fetch width")
-
- renameToDecodeDelay = Param.Unsigned(1, "Rename to decode delay")
- iewToDecodeDelay = Param.Unsigned(1, "Issue/Execute/Writeback to decode "
- "delay")
- commitToDecodeDelay = Param.Unsigned(1, "Commit to decode delay")
- fetchToDecodeDelay = Param.Unsigned(1, "Fetch to decode delay")
- decodeWidth = Param.Unsigned(8, "Decode width")
-
- iewToRenameDelay = Param.Unsigned(1, "Issue/Execute/Writeback to rename "
- "delay")
- commitToRenameDelay = Param.Unsigned(1, "Commit to rename delay")
- decodeToRenameDelay = Param.Unsigned(1, "Decode to rename delay")
- renameWidth = Param.Unsigned(8, "Rename width")
-
- commitToIEWDelay = Param.Unsigned(1, "Commit to "
- "Issue/Execute/Writeback delay")
- renameToIEWDelay = Param.Unsigned(2, "Rename to "
- "Issue/Execute/Writeback delay")
- issueToExecuteDelay = Param.Unsigned(1, "Issue to execute delay (internal "
- "to the IEW stage)")
- dispatchWidth = Param.Unsigned(8, "Dispatch width")
- issueWidth = Param.Unsigned(8, "Issue width")
- wbWidth = Param.Unsigned(8, "Writeback width")
- wbDepth = Param.Unsigned(1, "Writeback depth")
- fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
-
- iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
- "delay")
- renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
- commitWidth = Param.Unsigned(8, "Commit width")
- squashWidth = Param.Unsigned(8, "Squash width")
- trapLatency = Param.Tick(13, "Trap latency")
- fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
-
- backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
- forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
-
- predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')")
- localPredictorSize = Param.Unsigned(2048, "Size of local predictor")
- localCtrBits = Param.Unsigned(2, "Bits per counter")
- localHistoryTableSize = Param.Unsigned(2048, "Size of local history table")
- localHistoryBits = Param.Unsigned(11, "Bits for the local history")
- globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
- globalCtrBits = Param.Unsigned(2, "Bits per counter")
- globalHistoryBits = Param.Unsigned(13, "Bits of history")
- choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
- choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
-
- BTBEntries = Param.Unsigned(4096, "Number of BTB entries")
- BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits")
-
- RASSize = Param.Unsigned(16, "RAS size")
-
- LQEntries = Param.Unsigned(32, "Number of load queue entries")
- SQEntries = Param.Unsigned(32, "Number of store queue entries")
- LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
- SSITSize = Param.Unsigned(1024, "Store set ID table size")
-
- numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
-
- numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
- numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
- "registers")
- numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
- numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
-
- instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
-
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
-
- smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads")
- smtFetchPolicy = Param.String("SMT Fetch policy")
- smtLSQPolicy = Param.String("SMT LSQ Sharing Policy")
- smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter")
- smtIQPolicy = Param.String("SMT IQ Sharing Policy")
- smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter")
- smtROBPolicy = Param.String("SMT ROB Sharing Policy")
- smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter")
- smtCommitPolicy = Param.String("SMT Commit Policy")
-
- def addPrivateSplitL1Caches(self, ic, dc):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
- self.icache.tgts_per_mshr = 20
- self.dcache.tgts_per_mshr = 20
diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py
deleted file mode 100644
index 0913e044c..000000000
--- a/src/python/m5/objects/OzoneCPU.py
+++ /dev/null
@@ -1,95 +0,0 @@
-from m5.params import *
-from m5 import build_env
-from BaseCPU import BaseCPU
-
-class DerivOzoneCPU(BaseCPU):
- type = 'DerivOzoneCPU'
-
- numThreads = Param.Unsigned("number of HW thread contexts")
-
- checker = Param.BaseCPU("Checker CPU")
- if build_env['FULL_SYSTEM']:
- profile = Param.Latency('0ns', "trace the kernel stack")
-
- icache_port = Port("Instruction Port")
- dcache_port = Port("Data Port")
-
- width = Param.Unsigned("Width")
- frontEndWidth = Param.Unsigned("Front end width")
- frontEndLatency = Param.Unsigned("Front end latency")
- backEndWidth = Param.Unsigned("Back end width")
- backEndSquashLatency = Param.Unsigned("Back end squash latency")
- backEndLatency = Param.Unsigned("Back end latency")
- maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
- maxOutstandingMemOps = Param.Unsigned("Maximum number of outstanding memory operations")
- decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
- renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
- iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
- "delay")
- commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
- fetchWidth = Param.Unsigned("Fetch width")
-
- renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
- iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
- "delay")
- commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
- fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
- decodeWidth = Param.Unsigned("Decode width")
-
- iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
- "delay")
- commitToRenameDelay = Param.Unsigned("Commit to rename delay")
- decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
- renameWidth = Param.Unsigned("Rename width")
-
- commitToIEWDelay = Param.Unsigned("Commit to "
- "Issue/Execute/Writeback delay")
- renameToIEWDelay = Param.Unsigned("Rename to "
- "Issue/Execute/Writeback delay")
- issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
- "to the IEW stage)")
- issueWidth = Param.Unsigned("Issue width")
- executeWidth = Param.Unsigned("Execute width")
- executeIntWidth = Param.Unsigned("Integer execute width")
- executeFloatWidth = Param.Unsigned("Floating point execute width")
- executeBranchWidth = Param.Unsigned("Branch execute width")
- executeMemoryWidth = Param.Unsigned("Memory execute width")
-
- iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
- "delay")
- renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
- commitWidth = Param.Unsigned("Commit width")
- squashWidth = Param.Unsigned("Squash width")
-
- predType = Param.String("Type of branch predictor ('local', 'tournament')")
- localPredictorSize = Param.Unsigned("Size of local predictor")
- localCtrBits = Param.Unsigned("Bits per counter")
- localHistoryTableSize = Param.Unsigned("Size of local history table")
- localHistoryBits = Param.Unsigned("Bits for the local history")
- globalPredictorSize = Param.Unsigned("Size of global predictor")
- globalCtrBits = Param.Unsigned("Bits per counter")
- globalHistoryBits = Param.Unsigned("Bits of history")
- choicePredictorSize = Param.Unsigned("Size of choice predictor")
- choiceCtrBits = Param.Unsigned("Bits of choice counters")
-
- BTBEntries = Param.Unsigned("Number of BTB entries")
- BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
-
- RASSize = Param.Unsigned("RAS size")
-
- LQEntries = Param.Unsigned("Number of load queue entries")
- SQEntries = Param.Unsigned("Number of store queue entries")
- lsqLimits = Param.Bool(True, "LSQ size limits dispatch")
- LFSTSize = Param.Unsigned("Last fetched store table size")
- SSITSize = Param.Unsigned("Store set ID table size")
-
- numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
- numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
- "registers")
- numIQEntries = Param.Unsigned("Number of instruction queue entries")
- numROBEntries = Param.Unsigned("Number of reorder buffer entries")
-
- instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
-
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/python/m5/objects/Pci.py b/src/python/m5/objects/Pci.py
deleted file mode 100644
index 9d40adbfe..000000000
--- a/src/python/m5/objects/Pci.py
+++ /dev/null
@@ -1,59 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, DmaDevice, PioDevice
-
-class PciConfigData(SimObject):
- type = 'PciConfigData'
- VendorID = Param.UInt16("Vendor ID")
- DeviceID = Param.UInt16("Device ID")
- Command = Param.UInt16(0, "Command")
- Status = Param.UInt16(0, "Status")
- Revision = Param.UInt8(0, "Device")
- ProgIF = Param.UInt8(0, "Programming Interface")
- SubClassCode = Param.UInt8(0, "Sub-Class Code")
- ClassCode = Param.UInt8(0, "Class Code")
- CacheLineSize = Param.UInt8(0, "System Cacheline Size")
- LatencyTimer = Param.UInt8(0, "PCI Latency Timer")
- HeaderType = Param.UInt8(0, "PCI Header Type")
- BIST = Param.UInt8(0, "Built In Self Test")
-
- BAR0 = Param.UInt32(0x00, "Base Address Register 0")
- BAR1 = Param.UInt32(0x00, "Base Address Register 1")
- BAR2 = Param.UInt32(0x00, "Base Address Register 2")
- BAR3 = Param.UInt32(0x00, "Base Address Register 3")
- BAR4 = Param.UInt32(0x00, "Base Address Register 4")
- BAR5 = Param.UInt32(0x00, "Base Address Register 5")
- BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size")
- BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size")
- BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size")
- BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size")
- BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size")
- BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size")
-
- CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
- SubsystemID = Param.UInt16(0x00, "Subsystem ID")
- SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID")
- ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address")
- InterruptLine = Param.UInt8(0x00, "Interrupt Line")
- InterruptPin = Param.UInt8(0x00, "Interrupt Pin")
- MaximumLatency = Param.UInt8(0x00, "Maximum Latency")
- MinimumGrant = Param.UInt8(0x00, "Minimum Grant")
-
-class PciConfigAll(PioDevice):
- type = 'PciConfigAll'
- pio_latency = Param.Tick(1, "Programmed IO latency in simticks")
- bus = Param.UInt8(0x00, "PCI bus to act as config space for")
- size = Param.MemorySize32('16MB', "Size of config space")
-
-
-class PciDevice(DmaDevice):
- type = 'PciDevice'
- abstract = True
- config = Port(Self.pio.peerObj.port, "PCI configuration space port")
- pci_bus = Param.Int("PCI bus")
- pci_dev = Param.Int("PCI device number")
- pci_func = Param.Int("PCI function code")
- pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks")
- configdata = Param.PciConfigData(Parent.any, "PCI Config data")
- config_latency = Param.Latency('20ns', "Config read or write latency")
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
deleted file mode 100644
index 83dbc7710..000000000
--- a/src/python/m5/objects/PhysicalMemory.py
+++ /dev/null
@@ -1,29 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from MemObject import *
-
-class PhysicalMemory(MemObject):
- type = 'PhysicalMemory'
- port = VectorPort("the access port")
- range = Param.AddrRange(AddrRange('128MB'), "Device Address")
- file = Param.String('', "memory mapped file")
- latency = Param.Latency('1t', "latency of an access")
- zero = Param.Bool(False, "zero initialize memory")
-
-class DRAMMemory(PhysicalMemory):
- type = 'DRAMMemory'
- # Many of these should be observed from the configuration
- cpu_ratio = Param.Int(5,"ratio between CPU speed and memory bus speed")
- mem_type = Param.String("SDRAM", "Type of DRAM (DRDRAM, SDRAM)")
- mem_actpolicy = Param.String("open", "Open/Close policy")
- memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
- bus_width = Param.Int(16, "")
- act_lat = Param.Int(2, "RAS to CAS delay")
- cas_lat = Param.Int(1, "CAS delay")
- war_lat = Param.Int(2, "write after read delay")
- pre_lat = Param.Int(2, "precharge delay")
- dpl_lat = Param.Int(2, "data in to precharge delay")
- trc_lat = Param.Int(6, "row cycle delay")
- num_banks = Param.Int(4, "Number of Banks")
- num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")
-
diff --git a/src/python/m5/objects/Platform.py b/src/python/m5/objects/Platform.py
deleted file mode 100644
index ab2083eea..000000000
--- a/src/python/m5/objects/Platform.py
+++ /dev/null
@@ -1,7 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class Platform(SimObject):
- type = 'Platform'
- abstract = True
- intrctrl = Param.IntrControl(Parent.any, "interrupt controller")
diff --git a/src/python/m5/objects/Process.py b/src/python/m5/objects/Process.py
deleted file mode 100644
index 79268e6f4..000000000
--- a/src/python/m5/objects/Process.py
+++ /dev/null
@@ -1,36 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class Process(SimObject):
- type = 'Process'
- abstract = True
- output = Param.String('cout', 'filename for stdout/stderr')
- system = Param.System(Parent.any, "system process will run on")
-
-class LiveProcess(Process):
- type = 'LiveProcess'
- executable = Param.String('', "executable (overrides cmd[0] if set)")
- cmd = VectorParam.String("command line (executable plus arguments)")
- env = VectorParam.String('', "environment settings")
- cwd = Param.String('', "current working directory")
- input = Param.String('cin', "filename for stdin")
- uid = Param.Int(100, 'user id')
- euid = Param.Int(100, 'effective user id')
- gid = Param.Int(100, 'group id')
- egid = Param.Int(100, 'effective group id')
- pid = Param.Int(100, 'process id')
- ppid = Param.Int(99, 'parent process id')
-
-class AlphaLiveProcess(LiveProcess):
- type = 'AlphaLiveProcess'
-
-class SparcLiveProcess(LiveProcess):
- type = 'SparcLiveProcess'
-
-class MipsLiveProcess(LiveProcess):
- type = 'MipsLiveProcess'
-
-class EioProcess(Process):
- type = 'EioProcess'
- chkpt = Param.String('', "EIO checkpoint file name (optional)")
- file = Param.String("EIO trace file name")
diff --git a/src/python/m5/objects/Repl.py b/src/python/m5/objects/Repl.py
deleted file mode 100644
index b76aa1d6e..000000000
--- a/src/python/m5/objects/Repl.py
+++ /dev/null
@@ -1,11 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class Repl(SimObject):
- type = 'Repl'
- abstract = True
-
-class GenRepl(Repl):
- type = 'GenRepl'
- fresh_res = Param.Int("Fresh pool residency time")
- num_pools = Param.Int("Number of priority pools")
- pool_res = Param.Int("Pool residency time")
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
deleted file mode 100644
index 2b0e736e7..000000000
--- a/src/python/m5/objects/Root.py
+++ /dev/null
@@ -1,6 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-
-class Root(SimObject):
- type = 'Root'
- dummy = Param.Int(0, "We don't support objects without params")
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
deleted file mode 100644
index dfad18eb6..000000000
--- a/src/python/m5/objects/SimConsole.py
+++ /dev/null
@@ -1,11 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-
-class SimConsole(SimObject):
- type = 'SimConsole'
- append_name = Param.Bool(True, "append name() to filename")
- intr_control = Param.IntrControl(Parent.any, "interrupt controller")
- port = Param.TcpPort(3456, "listen port")
- number = Param.Int(0, "console number")
- output = Param.String('console', "file to dump output to")
diff --git a/src/python/m5/objects/SimpleDisk.py b/src/python/m5/objects/SimpleDisk.py
deleted file mode 100644
index 099a77dbb..000000000
--- a/src/python/m5/objects/SimpleDisk.py
+++ /dev/null
@@ -1,7 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-class SimpleDisk(SimObject):
- type = 'SimpleDisk'
- disk = Param.DiskImage("Disk Image")
- system = Param.System(Parent.any, "Sysetm Pointer")
diff --git a/src/python/m5/objects/SimpleOzoneCPU.py b/src/python/m5/objects/SimpleOzoneCPU.py
deleted file mode 100644
index 193f31b0f..000000000
--- a/src/python/m5/objects/SimpleOzoneCPU.py
+++ /dev/null
@@ -1,87 +0,0 @@
-from m5.params import *
-from m5 import build_env
-from BaseCPU import BaseCPU
-
-class SimpleOzoneCPU(BaseCPU):
- type = 'SimpleOzoneCPU'
-
- numThreads = Param.Unsigned("number of HW thread contexts")
-
- if not build_env['FULL_SYSTEM']:
- mem = Param.FunctionalMemory(NULL, "memory")
-
- width = Param.Unsigned("Width")
- frontEndWidth = Param.Unsigned("Front end width")
- backEndWidth = Param.Unsigned("Back end width")
- backEndSquashLatency = Param.Unsigned("Back end squash latency")
- backEndLatency = Param.Unsigned("Back end latency")
- maxInstBufferSize = Param.Unsigned("Maximum instruction buffer size")
- decodeToFetchDelay = Param.Unsigned("Decode to fetch delay")
- renameToFetchDelay = Param.Unsigned("Rename to fetch delay")
- iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch "
- "delay")
- commitToFetchDelay = Param.Unsigned("Commit to fetch delay")
- fetchWidth = Param.Unsigned("Fetch width")
-
- renameToDecodeDelay = Param.Unsigned("Rename to decode delay")
- iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode "
- "delay")
- commitToDecodeDelay = Param.Unsigned("Commit to decode delay")
- fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay")
- decodeWidth = Param.Unsigned("Decode width")
-
- iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename "
- "delay")
- commitToRenameDelay = Param.Unsigned("Commit to rename delay")
- decodeToRenameDelay = Param.Unsigned("Decode to rename delay")
- renameWidth = Param.Unsigned("Rename width")
-
- commitToIEWDelay = Param.Unsigned("Commit to "
- "Issue/Execute/Writeback delay")
- renameToIEWDelay = Param.Unsigned("Rename to "
- "Issue/Execute/Writeback delay")
- issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal "
- "to the IEW stage)")
- issueWidth = Param.Unsigned("Issue width")
- executeWidth = Param.Unsigned("Execute width")
- executeIntWidth = Param.Unsigned("Integer execute width")
- executeFloatWidth = Param.Unsigned("Floating point execute width")
- executeBranchWidth = Param.Unsigned("Branch execute width")
- executeMemoryWidth = Param.Unsigned("Memory execute width")
-
- iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit "
- "delay")
- renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay")
- commitWidth = Param.Unsigned("Commit width")
- squashWidth = Param.Unsigned("Squash width")
-
- localPredictorSize = Param.Unsigned("Size of local predictor")
- localCtrBits = Param.Unsigned("Bits per counter")
- localHistoryTableSize = Param.Unsigned("Size of local history table")
- localHistoryBits = Param.Unsigned("Bits for the local history")
- globalPredictorSize = Param.Unsigned("Size of global predictor")
- globalCtrBits = Param.Unsigned("Bits per counter")
- globalHistoryBits = Param.Unsigned("Bits of history")
- choicePredictorSize = Param.Unsigned("Size of choice predictor")
- choiceCtrBits = Param.Unsigned("Bits of choice counters")
-
- BTBEntries = Param.Unsigned("Number of BTB entries")
- BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits")
-
- RASSize = Param.Unsigned("RAS size")
-
- LQEntries = Param.Unsigned("Number of load queue entries")
- SQEntries = Param.Unsigned("Number of store queue entries")
- LFSTSize = Param.Unsigned("Last fetched store table size")
- SSITSize = Param.Unsigned("Store set ID table size")
-
- numPhysIntRegs = Param.Unsigned("Number of physical integer registers")
- numPhysFloatRegs = Param.Unsigned("Number of physical floating point "
- "registers")
- numIQEntries = Param.Unsigned("Number of instruction queue entries")
- numROBEntries = Param.Unsigned("Number of reorder buffer entries")
-
- instShiftAmt = Param.Unsigned("Number of bits to shift instructions by")
-
- function_trace = Param.Bool(False, "Enable function trace")
- function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/python/m5/objects/SparcTLB.py b/src/python/m5/objects/SparcTLB.py
deleted file mode 100644
index 06d2a8231..000000000
--- a/src/python/m5/objects/SparcTLB.py
+++ /dev/null
@@ -1,14 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-class SparcTLB(SimObject):
- type = 'SparcTLB'
- abstract = True
- size = Param.Int("TLB size")
-
-class SparcDTB(SparcTLB):
- type = 'SparcDTB'
- size = 64
-
-class SparcITB(SparcTLB):
- type = 'SparcITB'
- size = 64
diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py
deleted file mode 100644
index 810a320be..000000000
--- a/src/python/m5/objects/System.py
+++ /dev/null
@@ -1,68 +0,0 @@
-from m5.SimObject import SimObject
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from PhysicalMemory import *
-
-class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
-
-class System(SimObject):
- type = 'System'
- physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
- mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
- if build_env['FULL_SYSTEM']:
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
- "boot processor frequency")
- init_param = Param.UInt64(0, "numerical value to pass into simulator")
- boot_osflags = Param.String("a", "boot flags to pass to the kernel")
- kernel = Param.String("", "file that contains the kernel code")
- readfile = Param.String("", "file to read startup script from")
- symbolfile = Param.String("", "file to get the symbols from")
-
-class AlphaSystem(System):
- type = 'AlphaSystem'
- console = Param.String("file that contains the console code")
- pal = Param.String("file that contains palcode")
- system_type = Param.UInt64("Type of system we are emulating")
- system_rev = Param.UInt64("Revision of system we are emulating")
-
-class SparcSystem(System):
- type = 'SparcSystem'
- _rom_base = 0xfff0000000
- _nvram_base = 0x1f11000000
- _hypervisor_desc_base = 0x1f12080000
- _partition_desc_base = 0x1f12000000
- # ROM for OBP/Reset/Hypervisor
- rom = Param.PhysicalMemory(PhysicalMemory(range = AddrRange(_rom_base, size = '8MB')),
- "Memory to hold the ROM data")
- # nvram
- nvram = Param.PhysicalMemory(
- PhysicalMemory(range = AddrRange(_nvram_base, size = '8kB')),
- "Memory to hold the nvram data")
- # hypervisor description
- hypervisor_desc = Param.PhysicalMemory(
- PhysicalMemory(range = AddrRange(_hypervisor_desc_base, size = '8kB')),
- "Memory to hold the hypervisor description")
- # partition description
- partition_desc = Param.PhysicalMemory(
- PhysicalMemory(range = AddrRange(_partition_desc_base, size = '8kB')),
- "Memory to hold the partition description")
-
- reset_addr = Param.Addr(_rom_base, "Address to load ROM at")
- hypervisor_addr = Param.Addr(Addr('64kB') + _rom_base,
- "Address to load hypervisor at")
- openboot_addr = Param.Addr(Addr('512kB') + _rom_base,
- "Address to load openboot at")
- nvram_addr = Param.Addr(_nvram_base, "Address to put the nvram")
- hypervisor_desc_addr = Param.Addr(_hypervisor_desc_base,
- "Address for the hypervisor description")
- partition_desc_addr = Param.Addr(_partition_desc_base,
- "Address for the partition description")
-
- reset_bin = Param.String("file that contains the reset code")
- hypervisor_bin = Param.String("file that contains the hypervisor code")
- openboot_bin = Param.String("file that contains the openboot code")
- nvram_bin = Param.String("file that contains the contents of nvram")
- hypervisor_desc_bin = Param.String("file that contains the hypervisor description")
- partition_desc_bin = Param.String("file that contains the partition description")
-
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
deleted file mode 100644
index 0acfa0920..000000000
--- a/src/python/m5/objects/T1000.py
+++ /dev/null
@@ -1,106 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Uart import Uart8250
-from Platform import Platform
-from SimConsole import SimConsole
-
-
-class MmDisk(BasicPioDevice):
- type = 'MmDisk'
- image = Param.DiskImage("Disk Image")
- pio_addr = 0x1F40000000
-
-class DumbTOD(BasicPioDevice):
- type = 'DumbTOD'
- time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
- pio_addr = 0xfff0c1fff8
-
-class Iob(PioDevice):
- type = 'Iob'
- pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
-
-
-class T1000(Platform):
- type = 'T1000'
- system = Param.System(Parent.any, "system")
-
- fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
- #warn_access="Accessing Clock Unit -- Unimplemented!")
-
- fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
- ret_data64=0x0000000000000000, update_data=False)
- #warn_access="Accessing Memory Banks -- Unimplemented!")
-
- fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
- #warn_access="Accessing JBI -- Unimplemented!")
-
- fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
- ret_data64=0x0000000000000001, update_data=True)
- #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
-
- fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
- ret_data64=0x0000000000000000, update_data=True)
- #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
-
- fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
- #warn_access="Accessing SSI -- Unimplemented!")
-
- hconsole = SimConsole()
- hvuart = Uart8250(pio_addr=0xfff0c2c000)
- htod = DumbTOD()
-
- pconsole = SimConsole()
- puart0 = Uart8250(pio_addr=0x1f10000000)
-
- iob = Iob()
- # Attach I/O devices that are on chip
- def attachOnChipIO(self, bus):
- self.iob.pio = bus.port
- self.htod.pio = bus.port
-
-
- # Attach I/O devices to specified bus object. Can't do this
- # earlier, since the bus object itself is typically defined at the
- # System level.
- def attachIO(self, bus):
- self.hvuart.sim_console = self.hconsole
- self.puart0.sim_console = self.pconsole
- self.fake_clk.pio = bus.port
- self.fake_membnks.pio = bus.port
- self.fake_l2_1.pio = bus.port
- self.fake_l2_2.pio = bus.port
- self.fake_l2_3.pio = bus.port
- self.fake_l2_4.pio = bus.port
- self.fake_l2esr_1.pio = bus.port
- self.fake_l2esr_2.pio = bus.port
- self.fake_l2esr_3.pio = bus.port
- self.fake_l2esr_4.pio = bus.port
- self.fake_ssi.pio = bus.port
- self.fake_jbi.pio = bus.port
- self.puart0.pio = bus.port
- self.hvuart.pio = bus.port
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
deleted file mode 100644
index 85105ff20..000000000
--- a/src/python/m5/objects/Tsunami.py
+++ /dev/null
@@ -1,95 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from Device import BasicPioDevice, IsaFake, BadAddr
-from Platform import Platform
-from AlphaConsole import AlphaConsole
-from Uart import Uart8250
-from Pci import PciConfigAll
-from BadDevice import BadDevice
-
-class TsunamiCChip(BasicPioDevice):
- type = 'TsunamiCChip'
- tsunami = Param.Tsunami(Parent.any, "Tsunami")
-
-class TsunamiIO(BasicPioDevice):
- type = 'TsunamiIO'
- time = Param.Time('01/01/2009',
- "System time to use ('Now' for actual time)")
- year_is_bcd = Param.Bool(False,
- "The RTC should interpret the year as a BCD value")
- tsunami = Param.Tsunami(Parent.any, "Tsunami")
- frequency = Param.Frequency('1024Hz', "frequency of interrupts")
-
-class TsunamiPChip(BasicPioDevice):
- type = 'TsunamiPChip'
- tsunami = Param.Tsunami(Parent.any, "Tsunami")
-
-class Tsunami(Platform):
- type = 'Tsunami'
- system = Param.System(Parent.any, "system")
-
- cchip = TsunamiCChip(pio_addr=0x801a0000000)
- pchip = TsunamiPChip(pio_addr=0x80180000000)
- pciconfig = PciConfigAll()
- fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
-
- fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
- fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
- fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
- fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
-
- fake_ppc = IsaFake(pio_addr=0x801fc0003bb)
-
- fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
-
- fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
- fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
- fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
- fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
- fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
- fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
- fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
- fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
- fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
- fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
-
- fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
- fake_ata1 = IsaFake(pio_addr=0x801fc000170)
-
- fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
- io = TsunamiIO(pio_addr=0x801fc000000)
- uart = Uart8250(pio_addr=0x801fc0003f8)
- console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
-
- # Attach I/O devices to specified bus object. Can't do this
- # earlier, since the bus object itself is typically defined at the
- # System level.
- def attachIO(self, bus):
- self.cchip.pio = bus.port
- self.pchip.pio = bus.port
- self.pciconfig.pio = bus.default
- bus.responder_set = True
- bus.responder = self.pciconfig
- self.fake_sm_chip.pio = bus.port
- self.fake_uart1.pio = bus.port
- self.fake_uart2.pio = bus.port
- self.fake_uart3.pio = bus.port
- self.fake_uart4.pio = bus.port
- self.fake_ppc.pio = bus.port
- self.fake_OROM.pio = bus.port
- self.fake_pnp_addr.pio = bus.port
- self.fake_pnp_write.pio = bus.port
- self.fake_pnp_read0.pio = bus.port
- self.fake_pnp_read1.pio = bus.port
- self.fake_pnp_read2.pio = bus.port
- self.fake_pnp_read3.pio = bus.port
- self.fake_pnp_read4.pio = bus.port
- self.fake_pnp_read5.pio = bus.port
- self.fake_pnp_read6.pio = bus.port
- self.fake_pnp_read7.pio = bus.port
- self.fake_ata0.pio = bus.port
- self.fake_ata1.pio = bus.port
- self.fb.pio = bus.port
- self.io.pio = bus.port
- self.uart.pio = bus.port
- self.console.pio = bus.port
diff --git a/src/python/m5/objects/Uart.py b/src/python/m5/objects/Uart.py
deleted file mode 100644
index 62062c6b1..000000000
--- a/src/python/m5/objects/Uart.py
+++ /dev/null
@@ -1,17 +0,0 @@
-from m5.params import *
-from m5.proxy import *
-from m5 import build_env
-from Device import BasicPioDevice
-
-class Uart(BasicPioDevice):
- type = 'Uart'
- abstract = True
- sim_console = Param.SimConsole(Parent.any, "The console")
-
-class Uart8250(Uart):
- type = 'Uart8250'
-
-if build_env['ALPHA_TLASER']:
- class Uart8530(Uart):
- type = 'Uart8530'
-