diff options
Diffstat (limited to 'src/python/m5')
| -rw-r--r-- | src/python/m5/objects/AlphaO3CPU.py (renamed from src/python/m5/objects/AlphaFullCPU.py) | 4 | ||||
| -rw-r--r-- | src/python/m5/objects/FuncUnit.py | 17 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaO3CPU.py index 2988305d3..f14f8c88e 100644 --- a/src/python/m5/objects/AlphaFullCPU.py +++ b/src/python/m5/objects/AlphaO3CPU.py @@ -2,8 +2,8 @@ from m5 import build_env from m5.config import * from BaseCPU import BaseCPU -class DerivAlphaFullCPU(BaseCPU): - type = 'DerivAlphaFullCPU' +class DerivAlphaO3CPU(BaseCPU): + type = 'DerivAlphaO3CPU' activity = Param.Unsigned("Initial count") numThreads = Param.Unsigned("number of HW thread contexts") diff --git a/src/python/m5/objects/FuncUnit.py b/src/python/m5/objects/FuncUnit.py new file mode 100644 index 000000000..f61590ae9 --- /dev/null +++ b/src/python/m5/objects/FuncUnit.py @@ -0,0 +1,17 @@ +from m5.config import * + +class OpType(Enum): + vals = ['(null)', 'IntAlu', 'IntMult', 'IntDiv', 'FloatAdd', + 'FloatCmp', 'FloatCvt', 'FloatMult', 'FloatDiv', 'FloatSqrt', + 'MemRead', 'MemWrite', 'IprAccess', 'InstPrefetch'] + +class OpDesc(SimObject): + type = 'OpDesc' + issueLat = Param.Int(1, "cycles until another can be issued") + opClass = Param.OpType("type of operation") + opLat = Param.Int(1, "cycles until result is available") + +class FUDesc(SimObject): + type = 'FUDesc' + count = Param.Int("number of these FU's available") + opList = VectorParam.OpDesc("operation classes for this FU type") |