diff options
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/m5/__init__.py | 4 | ||||
| -rw-r--r-- | src/python/m5/objects/Tsunami.py | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py index d41fd5a61..42abfe2cc 100644 --- a/src/python/m5/__init__.py +++ b/src/python/m5/__init__.py @@ -171,10 +171,10 @@ def switchCpus(cpuList): for cpu in old_cpus: if not isinstance(cpu, objects.BaseCPU): - raise TypeError, "%s is not of type BaseCPU", cpu + raise TypeError, "%s is not of type BaseCPU" % cpu for cpu in new_cpus: if not isinstance(cpu, objects.BaseCPU): - raise TypeError, "%s is not of type BaseCPU", cpu + raise TypeError, "%s is not of type BaseCPU" % cpu # Drain all of the individual CPUs drain_event = cc_main.createCountedDrain() diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py index 78ab65b31..ffe93727b 100644 --- a/src/python/m5/objects/Tsunami.py +++ b/src/python/m5/objects/Tsunami.py @@ -76,6 +76,7 @@ class Tsunami(Platform): self.pchip.pio = bus.port self.pciconfig.pio = bus.default bus.responder_set = True + bus.responder = self.pciconfig self.fake_sm_chip.pio = bus.port self.fake_uart1.pio = bus.port self.fake_uart2.pio = bus.port |