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-rw-r--r--src/python/SConscript55
-rw-r--r--src/python/m5/SimObject.py24
-rw-r--r--src/python/m5/__init__.py106
-rw-r--r--src/python/m5/convert.py23
-rw-r--r--src/python/m5/event.py42
-rw-r--r--src/python/m5/main.py142
-rw-r--r--src/python/m5/objects/BaseCPU.py4
-rw-r--r--src/python/m5/objects/IntrControl.py2
-rw-r--r--src/python/m5/objects/PhysicalMemory.py2
-rw-r--r--src/python/m5/objects/Root.py19
-rw-r--r--src/python/m5/objects/SimConsole.py5
-rw-r--r--src/python/m5/objects/T1000.py27
-rw-r--r--src/python/m5/params.py136
-rw-r--r--src/python/m5/stats.py46
-rw-r--r--src/python/m5/ticks.py89
-rw-r--r--src/python/swig/core.i65
-rw-r--r--src/python/swig/event.i40
-rw-r--r--src/python/swig/pyevent.cc9
-rw-r--r--src/python/swig/pyevent.hh26
-rw-r--r--src/python/swig/pyobject.cc137
-rw-r--r--src/python/swig/pyobject.hh94
-rw-r--r--src/python/swig/random.i55
-rw-r--r--src/python/swig/sim_object.i101
-rw-r--r--src/python/swig/stats.i61
-rw-r--r--src/python/swig/trace.i76
25 files changed, 1142 insertions, 244 deletions
diff --git a/src/python/SConscript b/src/python/SConscript
index df1464809..6662c8a45 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -29,14 +29,14 @@
# Authors: Steve Reinhardt
# Nathan Binkert
-import os, os.path, re, sys
-from zipfile import PyZipFile
+import os
+import zipfile
# handy function for path joins
def join(*args):
return os.path.normpath(os.path.join(*args))
-Import('env')
+Import('*')
# This SConscript is in charge of collecting .py files and generating
# a zip archive that is appended to the m5 binary.
@@ -97,22 +97,59 @@ addPkg('m5')
pyzip_files.append('m5/defines.py')
pyzip_files.append('m5/info.py')
pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py'))
+pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py'))
-def swig_it(basename):
- env.Command(['swig/%s_wrap.cc' % basename, 'm5/internal/%s.py' % basename],
- 'swig/%s.i' % basename,
+swig_modules = []
+def swig_it(module):
+ env.Command(['swig/%s_wrap.cc' % module, 'm5/internal/%s.py' % module],
+ 'swig/%s.i' % module,
'$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
'-o ${TARGETS[0]} $SOURCES')
- pyzip_dep_files.append('m5/internal/%s.py' % basename)
+ swig_modules.append(module)
+ Source('swig/%s_wrap.cc' % module)
-swig_it('main')
+Source('swig/init.cc')
+Source('swig/pyevent.cc')
+Source('swig/pyobject.cc')
+
+swig_it('core')
swig_it('debug')
swig_it('event')
+swig_it('random')
+swig_it('sim_object')
+swig_it('stats')
+swig_it('trace')
+
+# Automatically generate m5/internals/__init__.py
+def MakeInternalsInit(target, source, env):
+ f = file(str(target[0]), 'w')
+ for m in swig_modules:
+ print >>f, 'import %s' % m
+ f.close()
+
+swig_py_files = [ 'm5/internal/%s.py' % m for m in swig_modules ]
+env.Command('m5/internal/__init__.py', swig_py_files, MakeInternalsInit)
+pyzip_dep_files.append('m5/internal/__init__.py')
+
+def MakeSwigInit(target, source, env):
+ f = file(str(target[0]), 'w')
+ print >>f, 'extern "C" {'
+ for m in swig_modules:
+ print >>f, ' void init_%s();' % m
+ print >>f, '}'
+ print >>f, 'void init_swig() {'
+ for m in swig_modules:
+ print >>f, ' init_%s();' % m
+ print >>f, '}'
+ f.close()
+
+swig_cc_files = [ 'swig/%s_wrap.cc' % m for m in swig_modules ]
+env.Command('swig/init.cc', swig_cc_files, MakeSwigInit)
# Action function to build the zip archive. Uses the PyZipFile module
# included in the standard Python library.
def buildPyZip(target, source, env):
- pzf = PyZipFile(str(target[0]), 'w')
+ pzf = zipfile.PyZipFile(str(target[0]), 'w')
for s in source:
pzf.writepy(str(s))
diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py
index 934358298..42266a80e 100644
--- a/src/python/m5/SimObject.py
+++ b/src/python/m5/SimObject.py
@@ -653,15 +653,13 @@ class SimObject(object):
instanceDict[self.path()] = self
- if hasattr(self, 'type') and not isinstance(self, ParamContext):
+ if hasattr(self, 'type'):
print 'type=%s' % self.type
child_names = self._children.keys()
child_names.sort()
- np_child_names = [c for c in child_names \
- if not isinstance(self._children[c], ParamContext)]
- if len(np_child_names):
- print 'children=%s' % ' '.join(np_child_names)
+ if len(child_names):
+ print 'children=%s' % ' '.join(child_names)
param_names = self._params.keys()
param_names.sort()
@@ -695,7 +693,7 @@ class SimObject(object):
def getCCObject(self):
if not self._ccObject:
self._ccObject = -1 # flag to catch cycles in recursion
- self._ccObject = internal.main.createSimObject(self.path())
+ self._ccObject = internal.sim_object.createSimObject(self.path())
elif self._ccObject == -1:
raise RuntimeError, "%s: recursive call to getCCObject()" \
% self.path()
@@ -711,8 +709,7 @@ class SimObject(object):
def startDrain(self, drain_event, recursive):
count = 0
- # ParamContexts don't serialize
- if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+ if isinstance(self, SimObject):
count += self._ccObject.drain(drain_event)
if recursive:
for child in self._children.itervalues():
@@ -720,7 +717,7 @@ class SimObject(object):
return count
def resume(self):
- if isinstance(self, SimObject) and not isinstance(self, ParamContext):
+ if isinstance(self, SimObject):
self._ccObject.resume()
for child in self._children.itervalues():
child.resume()
@@ -730,13 +727,13 @@ class SimObject(object):
# i don't know if there's a better way to do this - calling
# setMemoryMode directly from self._ccObject results in calling
# SimObject::setMemoryMode, not the System::setMemoryMode
- system_ptr = internal.main.convertToSystemPtr(self._ccObject)
+ system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject)
system_ptr.setMemoryMode(mode)
for child in self._children.itervalues():
child.changeTiming(mode)
def takeOverFrom(self, old_cpu):
- cpu_ptr = internal.main.convertToBaseCPUPtr(old_cpu._ccObject)
+ cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject)
self._ccObject.takeOverFrom(cpu_ptr)
# generate output file for 'dot' to display as a pretty graph.
@@ -782,9 +779,6 @@ class SimObject(object):
for c in self.children:
c.outputDot(dot)
-class ParamContext(SimObject):
- pass
-
# Function to provide to C++ so it can look up instances based on paths
def resolveSimObject(name):
obj = instanceDict[name]
@@ -793,7 +787,7 @@ def resolveSimObject(name):
# __all__ defines the list of symbols that get exported when
# 'from config import *' is invoked. Try to keep this reasonably
# short to avoid polluting other namespaces.
-__all__ = ['SimObject', 'ParamContext']
+__all__ = ['SimObject']
# see comment on imports at end of __init__.py.
import proxy
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index f39cc670a..06dc92bc6 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -27,14 +27,16 @@
# Authors: Nathan Binkert
# Steve Reinhardt
-import atexit, os, sys
+import atexit
+import os
+import sys
# import the SWIG-wrapped main C++ functions
import internal
# import a few SWIG-wrapped items (those that are likely to be used
# directly by user scripts) completely into this module for
# convenience
-from internal.main import simulate, SimLoopExitEvent
+import event
# import the m5 compile options
import defines
@@ -78,34 +80,72 @@ env.update(os.environ)
# The final hook to generate .ini files. Called from the user script
# once the config is built.
def instantiate(root):
- params.ticks_per_sec = float(root.clock.frequency)
+ # we need to fix the global frequency
+ ticks.fixGlobalFrequency()
+
root.unproxy_all()
# ugly temporary hack to get output to config.ini
sys.stdout = file(os.path.join(options.outdir, 'config.ini'), 'w')
root.print_ini()
sys.stdout.close() # close config.ini
sys.stdout = sys.__stdout__ # restore to original
- internal.main.loadIniFile(resolveSimObject) # load config.ini into C++
+
+ # load config.ini into C++
+ internal.core.loadIniFile(resolveSimObject)
+
+ # Initialize the global statistics
+ internal.stats.initSimStats()
+
+ # Create the C++ sim objects and connect ports
root.createCCObject()
root.connectPorts()
- internal.main.finalInit()
- noDot = True # temporary until we fix dot
- if not noDot:
- dot = pydot.Dot()
- instance.outputDot(dot)
- dot.orientation = "portrait"
- dot.size = "8.5,11"
- dot.ranksep="equally"
- dot.rank="samerank"
- dot.write("config.dot")
- dot.write_ps("config.ps")
+
+ # Do a second pass to finish initializing the sim objects
+ internal.sim_object.initAll()
+
+ # Do a third pass to initialize statistics
+ internal.sim_object.regAllStats()
+
+ # Check to make sure that the stats package is properly initialized
+ internal.stats.check()
+
+ # Reset to put the stats in a consistent state.
+ internal.stats.reset()
+
+def doDot(root):
+ dot = pydot.Dot()
+ instance.outputDot(dot)
+ dot.orientation = "portrait"
+ dot.size = "8.5,11"
+ dot.ranksep="equally"
+ dot.rank="samerank"
+ dot.write("config.dot")
+ dot.write_ps("config.ps")
+
+need_resume = []
+need_startup = True
+def simulate(*args, **kwargs):
+ global need_resume, need_startup
+
+ if need_startup:
+ internal.core.SimStartup()
+ need_startup = False
+
+ for root in need_resume:
+ resume(root)
+ need_resume = []
+
+ return internal.event.simulate(*args, **kwargs)
# Export curTick to user script.
def curTick():
- return internal.main.cvar.curTick
+ return internal.core.cvar.curTick
+
+# Python exit handlers happen in reverse order. We want to dump stats last.
+atexit.register(internal.stats.dump)
# register our C++ exit callback function with Python
-atexit.register(internal.main.doExitCleanup)
+atexit.register(internal.core.doExitCleanup)
# This loops until all objects have been fully drained.
def doDrain(root):
@@ -119,7 +159,7 @@ def doDrain(root):
# be drained.
def drain(root):
all_drained = False
- drain_event = internal.main.createCountedDrain()
+ drain_event = internal.event.createCountedDrain()
unready_objects = root.startDrain(drain_event, True)
# If we've got some objects that can't drain immediately, then simulate
if unready_objects > 0:
@@ -127,7 +167,7 @@ def drain(root):
simulate()
else:
all_drained = True
- internal.main.cleanupCountedDrain(drain_event)
+ internal.event.cleanupCountedDrain(drain_event)
return all_drained
def resume(root):
@@ -135,32 +175,32 @@ def resume(root):
def checkpoint(root, dir):
if not isinstance(root, objects.Root):
- raise TypeError, "Object is not a root object. Checkpoint must be called on a root object."
+ raise TypeError, "Checkpoint must be called on a root object."
doDrain(root)
print "Writing checkpoint"
- internal.main.serializeAll(dir)
+ internal.sim_object.serializeAll(dir)
resume(root)
def restoreCheckpoint(root, dir):
print "Restoring from checkpoint"
- internal.main.unserializeAll(dir)
- resume(root)
+ internal.sim_object.unserializeAll(dir)
+ need_resume.append(root)
def changeToAtomic(system):
- if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
- raise TypeError, "Object is not a root or system object. Checkpoint must be "
- "called on a root object."
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
doDrain(system)
print "Changing memory mode to atomic"
- system.changeTiming(internal.main.SimObject.Atomic)
+ system.changeTiming(internal.sim_object.SimObject.Atomic)
def changeToTiming(system):
- if not isinstance(system, objects.Root) and not isinstance(system, objects.System):
- raise TypeError, "Object is not a root or system object. Checkpoint must be "
- "called on a root object."
+ if not isinstance(system, (objects.Root, objects.System)):
+ raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
+ (type(system), objects.Root, objects.System)
doDrain(system)
print "Changing memory mode to timing"
- system.changeTiming(internal.main.SimObject.Timing)
+ system.changeTiming(internal.sim_object.SimObject.Timing)
def switchCpus(cpuList):
print "switching cpus"
@@ -180,7 +220,7 @@ def switchCpus(cpuList):
raise TypeError, "%s is not of type BaseCPU" % cpu
# Drain all of the individual CPUs
- drain_event = internal.main.createCountedDrain()
+ drain_event = internal.event.createCountedDrain()
unready_cpus = 0
for old_cpu in old_cpus:
unready_cpus += old_cpu.startDrain(drain_event, False)
@@ -188,7 +228,7 @@ def switchCpus(cpuList):
if unready_cpus > 0:
drain_event.setCount(unready_cpus)
simulate()
- internal.main.cleanupCountedDrain(drain_event)
+ internal.event.cleanupCountedDrain(drain_event)
# Now all of the CPUs are ready to be switched out
for old_cpu in old_cpus:
old_cpu._ccObject.switchOut()
diff --git a/src/python/m5/convert.py b/src/python/m5/convert.py
index 580a579bc..bb9e3e1f1 100644
--- a/src/python/m5/convert.py
+++ b/src/python/m5/convert.py
@@ -148,7 +148,7 @@ def toLatency(value):
raise ValueError, "cannot convert '%s' to latency" % value
-def toClockPeriod(value):
+def anyToLatency(value):
"""result is a clock period"""
if not isinstance(value, str):
@@ -170,6 +170,27 @@ def toClockPeriod(value):
raise ValueError, "cannot convert '%s' to clock period" % value
+def anyToFrequency(value):
+ """result is a clock period"""
+
+ if not isinstance(value, str):
+ raise TypeError, "wrong type '%s' should be str" % type(value)
+
+ try:
+ val = toFrequency(value)
+ return val
+ except ValueError:
+ pass
+
+ try:
+ val = toLatency(value)
+ if val != 0:
+ val = 1 / val
+ return val
+ except ValueError:
+ pass
+
+ raise ValueError, "cannot convert '%s' to clock period" % value
def toNetworkBandwidth(value):
if not isinstance(value, str):
diff --git a/src/python/m5/event.py b/src/python/m5/event.py
new file mode 100644
index 000000000..2d6497464
--- /dev/null
+++ b/src/python/m5/event.py
@@ -0,0 +1,42 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+from internal.event import create
+from internal.event import SimLoopExitEvent as SimExit
+
+class ProgressEvent(object):
+ def __init__(self, period):
+ self.period = int(period)
+ self.schedule()
+
+ def schedule(self):
+ create(self, m5.curTick() + self.period)
+
+ def __call__(self):
+ print "Progress! Time now %fs" % (m5.curTick()/1e12)
+ self.schedule()
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index 5df6d03cf..1695ed75f 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -29,11 +29,7 @@
import code, optparse, os, socket, sys
from datetime import datetime
from attrdict import attrdict
-
-try:
- import info
-except ImportError:
- info = None
+import traceflags
__all__ = [ 'options', 'arguments', 'main' ]
@@ -45,6 +41,19 @@ The Regents of The University of Michigan
All Rights Reserved
'''
+def print_list(items, indent=4):
+ line = ' ' * indent
+ for i,item in enumerate(items):
+ if len(line) + len(item) > 76:
+ print line
+ line = ' ' * indent
+
+ if i < len(items) - 1:
+ line += '%s, ' % item
+ else:
+ line += item
+ print line
+
# there's only one option parsing done, so make it global and add some
# helper functions to make it work well.
parser = optparse.OptionParser(usage=usage, version=version,
@@ -140,50 +149,17 @@ add_option("--debug-break", metavar="TIME[,TIME]", action='append', split=',',
# Tracing options
set_group("Trace Options")
+add_option("--trace-help", action='store_true',
+ help="Print help on trace flags")
add_option("--trace-flags", metavar="FLAG[,FLAG]", action='append', split=',',
- help="Sets the flags for tracing")
-add_option("--trace-start", metavar="TIME", default='0s',
- help="Start tracing at TIME (must have units)")
-add_option("--trace-cycle", metavar="CYCLE", default='0',
- help="Start tracing at CYCLE")
+ help="Sets the flags for tracing (-FLAG disables a flag)")
+add_option("--trace-start", metavar="TIME", type='int',
+ help="Start tracing at TIME (must be in ticks)")
add_option("--trace-file", metavar="FILE", default="cout",
help="Sets the output file for tracing [Default: %default]")
-add_option("--trace-circlebuf", metavar="SIZE", type="int", default=0,
- help="If SIZE is non-zero, turn on the circular buffer with SIZE lines")
-add_option("--no-trace-circlebuf", action="store_const", const=0,
- dest='trace_circlebuf', help=optparse.SUPPRESS_HELP)
-bool_option("trace-dumponexit", default=False,
- help="Dump trace buffer on exit")
add_option("--trace-ignore", metavar="EXPR", action='append', split=':',
help="Ignore EXPR sim objects")
-# Execution Trace options
-set_group("Execution Trace Options")
-bool_option("speculative", default=True,
- help="Don't capture speculative instructions")
-bool_option("print-cycle", default=True,
- help="Don't print cycle numbers in trace output")
-bool_option("print-symbol", default=True,
- help="Disable PC symbols in trace output")
-bool_option("print-opclass", default=True,
- help="Don't print op class type in trace output")
-bool_option("print-thread", default=True,
- help="Don't print thread number in trace output")
-bool_option("print-effaddr", default=True,
- help="Don't print effective address in trace output")
-bool_option("print-data", default=True,
- help="Don't print result data in trace output")
-bool_option("print-iregs", default=False,
- help="Print fetch sequence numbers in trace output")
-bool_option("print-fetch-seq", default=False,
- help="Print fetch sequence numbers in trace output")
-bool_option("print-cpseq", default=False,
- help="Print correct path sequence numbers in trace output")
-#bool_option("print-reg-delta", default=False,
-# help="Print which registers changed to what in trace output")
-bool_option("legion-lock", default=False,
- help="Compare simulator state with Legion simulator every cycle")
-
options = attrdict()
arguments = []
@@ -211,6 +187,9 @@ def parse_args():
return opts,args
def main():
+ import defines
+ import event
+ import info
import internal
parse_args()
@@ -242,6 +221,19 @@ def main():
print info.RELEASE_NOTES
print
+ if options.trace_help:
+ done = True
+ print "Base Flags:"
+ print_list(traceflags.baseFlags, indent=4)
+ print
+ print "Compound Flags:"
+ for flag in traceflags.compoundFlags:
+ if flag == 'All':
+ continue
+ print " %s:" % flag
+ print_list(traceflags.compoundFlagMap[flag], indent=8)
+ print
+
if done:
sys.exit(0)
@@ -249,7 +241,7 @@ def main():
print "M5 Simulator System"
print brief_copyright
print
- print "M5 compiled %s" % internal.main.cvar.compileDate;
+ print "M5 compiled %s" % internal.core.cvar.compileDate;
print "M5 started %s" % datetime.now().ctime()
print "M5 executing on %s" % socket.gethostname()
print "command line:",
@@ -261,10 +253,11 @@ def main():
if not arguments or not os.path.isfile(arguments[0]):
if arguments and not os.path.isfile(arguments[0]):
print "Script %s not found" % arguments[0]
+
usage(2)
# tell C++ about output directory
- internal.main.setOutputDir(options.outdir)
+ internal.core.setOutputDir(options.outdir)
# update the system path with elements from the -p option
sys.path[0:0] = options.path
@@ -272,34 +265,45 @@ def main():
import objects
# set stats options
- objects.Statistics.text_file = options.stats_file
+ internal.stats.initText(options.stats_file)
# set debugging options
for when in options.debug_break:
internal.debug.schedBreakCycle(int(when))
- # set tracing options
- objects.Trace.flags = options.trace_flags
- objects.Trace.start = options.trace_start
- objects.Trace.cycle = options.trace_cycle
- objects.Trace.file = options.trace_file
- objects.Trace.bufsize = options.trace_circlebuf
- objects.Trace.dump_on_exit = options.trace_dumponexit
- objects.Trace.ignore = options.trace_ignore
-
- # set execution trace options
- objects.ExecutionTrace.speculative = options.speculative
- objects.ExecutionTrace.print_cycle = options.print_cycle
- objects.ExecutionTrace.pc_symbol = options.print_symbol
- objects.ExecutionTrace.print_opclass = options.print_opclass
- objects.ExecutionTrace.print_thread = options.print_thread
- objects.ExecutionTrace.print_effaddr = options.print_effaddr
- objects.ExecutionTrace.print_data = options.print_data
- objects.ExecutionTrace.print_iregs = options.print_iregs
- objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
- objects.ExecutionTrace.print_cpseq = options.print_cpseq
- #objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
- objects.ExecutionTrace.legion_lockstep = options.legion_lock
+ on_flags = []
+ off_flags = []
+ for flag in options.trace_flags:
+ off = False
+ if flag.startswith('-'):
+ flag = flag[1:]
+ off = True
+ if flag not in traceflags.allFlags:
+ print >>sys.stderr, "invalid trace flag '%s'" % flag
+ sys.exit(1)
+
+ if off:
+ off_flags.append(flag)
+ else:
+ on_flags.append(flag)
+
+ for flag in on_flags:
+ internal.trace.set(flag)
+
+ for flag in off_flags:
+ internal.trace.clear(flag)
+
+ if options.trace_start:
+ def enable_trace():
+ internal.trace.cvar.enabled = True
+ event.create(enable_trace, int(options.trace_start))
+ else:
+ internal.trace.cvar.enabled = True
+
+ internal.trace.output(options.trace_file)
+
+ for ignore in options.trace_ignore:
+ internal.trace.ignore(ignore)
sys.argv = arguments
sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
@@ -309,7 +313,7 @@ def main():
# we want readline if we're doing anything interactive
if options.interactive or options.pdb:
- exec("import readline", scope)
+ exec "import readline" in scope
# if pdb was requested, execfile the thing under pdb, otherwise,
# just do the execfile normally
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 67a28a61e..986220c3f 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -47,8 +47,8 @@ class BaseCPU(SimObject):
defer_registration = Param.Bool(False,
"defer registration with system (for sampling)")
- clock = Param.Clock(Parent.clock, "clock speed")
- phase = Param.Latency("0ns", "clock phase")
+ clock = Param.Clock('1t', "clock speed")
+ phase = Param.Latency('0ns', "clock phase")
_mem_ports = []
diff --git a/src/python/m5/objects/IntrControl.py b/src/python/m5/objects/IntrControl.py
index a7cf5cc84..398ba47f9 100644
--- a/src/python/m5/objects/IntrControl.py
+++ b/src/python/m5/objects/IntrControl.py
@@ -3,4 +3,4 @@ from m5.params import *
from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
- cpu = Param.BaseCPU(Parent.cpu[0], "the cpu")
+ sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index b8df6229e..c389e4a7f 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -8,7 +8,7 @@ class PhysicalMemory(MemObject):
functional = Port("Functional Access Port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
- latency = Param.Latency(Parent.clock, "latency of an access")
+ latency = Param.Latency('1t', "latency of an access")
zero = Param.Bool(False, "zero initialize memory")
class DRAMMemory(PhysicalMemory):
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index b6123f192..2b0e736e7 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -1,23 +1,6 @@
from m5.SimObject import SimObject
from m5.params import *
-from Serialize import Serialize
-from Serialize import Statreset
-from Statistics import Statistics
-from Trace import Trace
-from ExeTrace import ExecutionTrace
class Root(SimObject):
type = 'Root'
- clock = Param.RootClock('1THz', "tick frequency")
- max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
- progress_interval = Param.Tick('0',
- "print a progress message every n ticks (0 = never)")
- output_file = Param.String('cout', "file to dump simulator output to")
- checkpoint = Param.String('', "checkpoint file to load")
-# stats = Param.Statistics(Statistics(), "statistics object")
-# trace = Param.Trace(Trace(), "trace object")
-# serialize = Param.Serialize(Serialize(), "checkpoint generation options")
- stats = Statistics()
- trace = Trace()
- exetrace = ExecutionTrace()
- serialize = Serialize()
+ dummy = Param.Int(0, "We don't support objects without params")
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index bdd7f246d..dfad18eb6 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,14 +1,11 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-class ConsoleListener(SimObject):
- type = 'ConsoleListener'
- port = Param.TcpPort(3456, "listen port")
class SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
- listener = Param.ConsoleListener("console listener")
+ port = Param.TcpPort(3456, "listen port")
number = Param.Int(0, "console number")
output = Param.String('console', "file to dump output to")
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 85c4db6df..0acfa0920 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -1,9 +1,9 @@
from m5.params import *
from m5.proxy import *
-from Device import BasicPioDevice, IsaFake, BadAddr
+from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
-from SimConsole import SimConsole, ConsoleListener
+from SimConsole import SimConsole
class MmDisk(BasicPioDevice):
@@ -16,6 +16,10 @@ class DumbTOD(BasicPioDevice):
time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
pio_addr = 0xfff0c1fff8
+class Iob(PioDevice):
+ type = 'Iob'
+ pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
+
class T1000(Platform):
type = 'T1000'
@@ -28,9 +32,6 @@ class T1000(Platform):
ret_data64=0x0000000000000000, update_data=False)
#warn_access="Accessing Memory Banks -- Unimplemented!")
- fake_iob = IsaFake(pio_addr=0x9800000000, pio_size=0x100000000)
- #warn_access="Accessing IOB -- Unimplemented!")
-
fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
#warn_access="Accessing JBI -- Unimplemented!")
@@ -69,20 +70,28 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
+ hconsole = SimConsole()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
+ pconsole = SimConsole()
puart0 = Uart8250(pio_addr=0x1f10000000)
- console = SimConsole(listener = ConsoleListener())
+
+ iob = Iob()
+ # Attach I/O devices that are on chip
+ def attachOnChipIO(self, bus):
+ self.iob.pio = bus.port
+ self.htod.pio = bus.port
+
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
# System level.
def attachIO(self, bus):
+ self.hvuart.sim_console = self.hconsole
+ self.puart0.sim_console = self.pconsole
self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port
- self.fake_iob.pio = bus.port
- self.fake_jbi.pio = bus.port
self.fake_l2_1.pio = bus.port
self.fake_l2_2.pio = bus.port
self.fake_l2_3.pio = bus.port
@@ -92,6 +101,6 @@ class T1000(Platform):
self.fake_l2esr_3.pio = bus.port
self.fake_l2esr_4.pio = bus.port
self.fake_ssi.pio = bus.port
+ self.fake_jbi.pio = bus.port
self.puart0.pio = bus.port
self.hvuart.pio = bus.port
- self.htod.pio = bus.port
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index f8a9f9ddd..9892df97c 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -51,6 +51,7 @@ import sys
import time
import convert
+import ticks
from util import *
# Dummy base class to identify types that are legitimate for SimObject
@@ -360,6 +361,7 @@ class MemorySize(CheckedInt):
self._check()
class MemorySize32(CheckedInt):
+ cxx_type = 'uint32_t'
size = 32
unsigned = True
def __init__(self, value):
@@ -632,47 +634,29 @@ class Enum(ParamValue):
def __str__(self):
return self.value
-ticks_per_sec = None
-
# how big does a rounding error need to be before we warn about it?
frequency_tolerance = 0.001 # 0.1%
-# convert a floting-point # of ticks to integer, and warn if rounding
-# discards too much precision
-def tick_check(float_ticks):
- if float_ticks == 0:
- return 0
- int_ticks = int(round(float_ticks))
- err = (float_ticks - int_ticks) / float_ticks
- if err > frequency_tolerance:
- print >> sys.stderr, "Warning: rounding error > tolerance"
- print >> sys.stderr, " %f rounded to %d" % (float_ticks, int_ticks)
- #raise ValueError
- return int_ticks
-
-def getLatency(value):
- if isinstance(value, Latency) or isinstance(value, Clock):
- return value.value
- elif isinstance(value, Frequency) or isinstance(value, RootClock):
- return 1 / value.value
- elif isinstance(value, str):
- try:
- return convert.toLatency(value)
- except ValueError:
- try:
- return 1 / convert.toFrequency(value)
- except ValueError:
- pass # fall through
- raise ValueError, "Invalid Frequency/Latency value '%s'" % value
-
-
-class Latency(NumericParamValue):
+class TickParamValue(NumericParamValue):
cxx_type = 'Tick'
cxx_predecls = ['#include "sim/host.hh"']
swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
'%import "sim/host.hh"']
+
+class Latency(TickParamValue):
def __init__(self, value):
- self.value = getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ self.ticks = value.ticks
+ self.value = value.value
+ elif isinstance(value, Frequency):
+ self.ticks = value.ticks
+ self.value = 1.0 / value.value
+ elif value.endswith('t'):
+ self.ticks = True
+ self.value = int(value[:-1])
+ else:
+ self.ticks = False
+ self.value = convert.toLatency(value)
def __getattr__(self, attr):
if attr in ('latency', 'period'):
@@ -683,15 +667,25 @@ class Latency(NumericParamValue):
# convert latency to ticks
def ini_str(self):
- return str(tick_check(self.value * ticks_per_sec))
+ if self.ticks or self.value == 0:
+ return '%d' % self.value
+ else:
+ return '%d' % (ticks.fromSeconds(self.value))
-class Frequency(NumericParamValue):
- cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
- '%import "sim/host.hh"']
+class Frequency(TickParamValue):
def __init__(self, value):
- self.value = 1 / getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ if value.value == 0:
+ self.value = 0
+ else:
+ self.value = 1.0 / value.value
+ self.ticks = value.ticks
+ elif isinstance(value, Frequency):
+ self.value = value.value
+ self.ticks = value.ticks
+ else:
+ self.ticks = False
+ self.value = convert.toFrequency(value)
def __getattr__(self, attr):
if attr == 'frequency':
@@ -700,30 +694,12 @@ class Frequency(NumericParamValue):
return Latency(self)
raise AttributeError, "Frequency object has no attribute '%s'" % attr
- # convert frequency to ticks per period
- def ini_str(self):
- return self.period.ini_str()
-
-# Just like Frequency, except ini_str() is absolute # of ticks per sec (Hz).
-# We can't inherit from Frequency because we don't want it to be directly
-# assignable to a regular Frequency parameter.
-class RootClock(ParamValue):
- cxx_type = 'Tick'
- cxx_predecls = ['#include "sim/host.hh"']
- swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
- '%import "sim/host.hh"']
- def __init__(self, value):
- self.value = 1 / getLatency(value)
-
- def __getattr__(self, attr):
- if attr == 'frequency':
- return Frequency(self)
- if attr in ('latency', 'period'):
- return Latency(self)
- raise AttributeError, "Frequency object has no attribute '%s'" % attr
-
+ # convert latency to ticks
def ini_str(self):
- return str(tick_check(self.value))
+ if self.ticks or self.value == 0:
+ return '%d' % self.value
+ else:
+ return '%d' % (ticks.fromSeconds(1.0 / self.value))
# A generic frequency and/or Latency value. Value is stored as a latency,
# but to avoid ambiguity this object does not support numeric ops (* or /).
@@ -734,7 +710,18 @@ class Clock(ParamValue):
swig_predecls = ['%import "python/m5/swig/stdint.i"\n' +
'%import "sim/host.hh"']
def __init__(self, value):
- self.value = getLatency(value)
+ if isinstance(value, (Latency, Clock)):
+ self.ticks = value.ticks
+ self.value = value.value
+ elif isinstance(value, Frequency):
+ self.ticks = value.ticks
+ self.value = 1.0 / value.value
+ elif value.endswith('t'):
+ self.ticks = True
+ self.value = int(value[:-1])
+ else:
+ self.ticks = False
+ self.value = convert.anyToLatency(value)
def __getattr__(self, attr):
if attr == 'frequency':
@@ -749,18 +736,23 @@ class Clock(ParamValue):
class NetworkBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(cls, value):
- val = convert.toNetworkBandwidth(value) / 8.0
+ # convert to bits per second
+ val = convert.toNetworkBandwidth(value)
return super(cls, NetworkBandwidth).__new__(cls, val)
def __str__(self):
return str(self.val)
def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
+ # convert to seconds per byte
+ value = 8.0 / float(self)
+ # convert to ticks per byte
+ return '%f' % (ticks.fromSeconds(value))
class MemoryBandwidth(float,ParamValue):
cxx_type = 'float'
def __new__(self, value):
+ # we want the number of ticks per byte of data
val = convert.toMemoryBandwidth(value)
return super(cls, MemoryBandwidth).__new__(cls, val)
@@ -768,7 +760,10 @@ class MemoryBandwidth(float,ParamValue):
return str(self.val)
def ini_str(self):
- return '%f' % (ticks_per_sec / float(self))
+ # convert to seconds per byte
+ value = 1.0 / float(self)
+ # convert to ticks per byte
+ return '%f' % (ticks.fromSeconds(value))
#
# "Constants"... handy aliases for various values.
@@ -894,9 +889,8 @@ class PortRef(object):
if self.ccConnected: # already done this
return
peer = self.peer
- internal.main.connectPorts(self.simobj.getCCObject(), self.name,
- self.index, peer.simobj.getCCObject(),
- peer.name, peer.index)
+ internal.sim_object.connectPorts(self.simobj.getCCObject(), self.name,
+ self.index, peer.simobj.getCCObject(), peer.name, peer.index)
self.ccConnected = True
peer.ccConnected = True
@@ -1024,7 +1018,7 @@ __all__ = ['Param', 'VectorParam',
'Counter', 'Addr', 'Tick', 'Percent',
'TcpPort', 'UdpPort', 'EthernetAddr',
'MemorySize', 'MemorySize32',
- 'Latency', 'Frequency', 'RootClock', 'Clock',
+ 'Latency', 'Frequency', 'Clock',
'NetworkBandwidth', 'MemoryBandwidth',
'Range', 'AddrRange', 'TickRange',
'MaxAddr', 'MaxTick', 'AllMemory',
diff --git a/src/python/m5/stats.py b/src/python/m5/stats.py
new file mode 100644
index 000000000..041a3f58d
--- /dev/null
+++ b/src/python/m5/stats.py
@@ -0,0 +1,46 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import internal
+
+from internal.stats import dump
+from internal.stats import initSimStats
+from internal.stats import reset
+from internal.stats import StatEvent as event
+
+def initText(filename, desc=True, compat=True):
+ internal.stats.initText(filename, desc, compat)
+
+def initMySQL(host, database, user='', passwd='', project='test', name='test',
+ sample='0'):
+ if not user:
+ import getpass
+ user = getpass.getuser()
+
+ internal.stats.initMySQL(host, database, user, passwd, project, name,
+ sample)
diff --git a/src/python/m5/ticks.py b/src/python/m5/ticks.py
new file mode 100644
index 000000000..e91b470ff
--- /dev/null
+++ b/src/python/m5/ticks.py
@@ -0,0 +1,89 @@
+# Copyright (c) 2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Nathan Binkert
+
+import sys
+
+import convert
+import internal
+
+tps = 1.0e12 # default to 1 THz (1 Tick == 1 ps)
+tps_fixed = False # once set to true, can't be changed
+
+# fix the global frequency and tell C++ about it
+def fixGlobalFrequency():
+ global tps, tps_fixed
+ if not tps_fixed:
+ tps_fixed = True
+ internal.core.setClockFrequency(int(tps))
+ print "Global frequency set at %d ticks per second" % int(tps)
+
+def setGlobalFrequency(ticksPerSecond):
+ global tps, tps_fixed
+
+ if tps_fixed:
+ raise AttributeError, \
+ "Global frequency already fixed at %f ticks/s." % tps
+
+ if isinstance(ticksPerSecond, (int, long)):
+ tps = ticksPerSecond
+ elif isinstance(ticksPerSecond, float):
+ tps = ticksPerSecond
+ elif isinstance(ticksPerSecond, str):
+ tps = round(convert.anyToFrequency(ticksPerSecond))
+ else:
+ raise TypeError, \
+ "wrong type '%s' for ticksPerSecond" % type(ticksPerSecond)
+
+# how big does a rounding error need to be before we warn about it?
+frequency_tolerance = 0.001 # 0.1%
+
+def fromSeconds(value):
+ if not isinstance(value, float):
+ raise TypeError, "can't convert '%s' to type tick" % type(value)
+
+ # once someone needs to convert to seconds, the global frequency
+ # had better be fixed
+ if not tps_fixed:
+ raise AttributeError, \
+ "In order to do conversions, the global frequency must be fixed"
+
+ if value == 0:
+ return 0
+
+ # convert the value from time to ticks
+ value *= tps
+
+ int_value = int(round(value))
+ err = (value - int_value) / value
+ if err > frequency_tolerance:
+ print >>sys.stderr, "Warning: rounding error > tolerance"
+ print >>sys.stderr, " %f rounded to %d" % (value, int_value)
+ return int_value
+
+__all__ = [ 'setGlobalFrequency', 'fixGlobalFrequency', 'fromSeconds',
+ 'frequency_tolerance' ]
diff --git a/src/python/swig/core.i b/src/python/swig/core.i
new file mode 100644
index 000000000..3edfa4c7e
--- /dev/null
+++ b/src/python/swig/core.i
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ * Steve Reinhardt
+ */
+
+%module core
+
+%{
+#include "python/swig/pyobject.hh"
+
+#include "sim/core.hh"
+#include "sim/host.hh"
+#include "sim/startup.hh"
+
+extern const char *compileDate;
+%}
+
+%include "stdint.i"
+%include "std_string.i"
+%include "sim/host.hh"
+
+void setOutputDir(const std::string &dir);
+void setOutputFile(const std::string &file);
+void loadIniFile(PyObject *);
+void SimStartup();
+void doExitCleanup();
+
+char *compileDate;
+
+void setClockFrequency(Tick ticksPerSecond);
+
+%immutable curTick;
+Tick curTick;
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._core"
+%}
diff --git a/src/python/swig/event.i b/src/python/swig/event.i
index 554c9fa0e..9a2093c99 100644
--- a/src/python/swig/event.i
+++ b/src/python/swig/event.i
@@ -33,19 +33,43 @@
%{
#include "python/swig/pyevent.hh"
-inline void
-create(PyObject *object, Tick when)
-{
- new PythonEvent(object, when);
-}
+#include "sim/sim_events.hh"
+#include "sim/sim_exit.hh"
+#include "sim/simulate.hh"
%}
%include "stdint.i"
+%include "std_string.i"
%include "sim/host.hh"
-%inline %{
-extern void create(PyObject *object, Tick when);
-%}
+void create(PyObject *object, Tick when);
+
+class Event;
+class CountedDrainEvent : public Event {
+ public:
+ void setCount(int _count);
+};
+
+CountedDrainEvent *createCountedDrain();
+void cleanupCountedDrain(Event *drain_event);
+
+// minimal definition of SimExitEvent interface to wrap
+class SimLoopExitEvent {
+ public:
+ std::string getCause();
+ int getCode();
+ SimLoopExitEvent(EventQueue *q, Tick _when, Tick _repeat,
+ const std::string &_cause, int c = 0);
+};
+
+%exception simulate {
+ $action
+ if (!result) {
+ return NULL;
+ }
+}
+SimLoopExitEvent *simulate(Tick num_cycles = MaxTick);
+void exitSimLoop(const std::string &message, int exit_code);
%wrapper %{
// fix up module name to reflect the fact that it's inside the m5 package
diff --git a/src/python/swig/pyevent.cc b/src/python/swig/pyevent.cc
index 6fb7d3f17..7f23b8874 100644
--- a/src/python/swig/pyevent.cc
+++ b/src/python/swig/pyevent.cc
@@ -31,6 +31,7 @@
#include <Python.h>
#include "python/swig/pyevent.hh"
+#include "sim/async.hh"
PythonEvent::PythonEvent(PyObject *obj, Tick when, Priority priority)
: Event(&mainEventQueue, priority), object(obj)
@@ -52,9 +53,9 @@ PythonEvent::~PythonEvent()
void
PythonEvent::process()
{
- PyObject *result;
-
- result = PyObject_CallMethod(object, "process", "");
+ PyObject *args = PyTuple_New(0);
+ PyObject *result = PyObject_Call(object, args, NULL);
+ Py_DECREF(args);
if (result) {
// Nothing to do just decrement the reference count
@@ -62,5 +63,7 @@ PythonEvent::process()
} else {
// Somethign should be done to signal back to the main interpreter
// that there's been an exception.
+ async_event = true;
+ async_exception = true;
}
}
diff --git a/src/python/swig/pyevent.hh b/src/python/swig/pyevent.hh
index 16af85a84..65e80e9e4 100644
--- a/src/python/swig/pyevent.hh
+++ b/src/python/swig/pyevent.hh
@@ -32,6 +32,7 @@
#define __PYTHON_SWIG_PYEVENT_HH__
#include "sim/eventq.hh"
+#include "sim/sim_events.hh"
class PythonEvent : public Event
{
@@ -45,4 +46,29 @@ class PythonEvent : public Event
virtual void process();
};
+inline void
+create(PyObject *object, Tick when)
+{
+ new PythonEvent(object, when);
+}
+
+inline Event *
+createCountedDrain()
+{
+ return new CountedDrainEvent();
+}
+
+inline void
+cleanupCountedDrain(Event *counted_drain)
+{
+ CountedDrainEvent *event =
+ dynamic_cast<CountedDrainEvent *>(counted_drain);
+ if (event == NULL) {
+ fatal("Called cleanupCountedDrain() on an event that was not "
+ "a CountedDrainEvent.");
+ }
+ assert(event->getCount() == 0);
+ delete event;
+}
+
#endif // __PYTHON_SWIG_PYEVENT_HH__
diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc
new file mode 100644
index 000000000..11141fa84
--- /dev/null
+++ b/src/python/swig/pyobject.cc
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <Python.h>
+
+#include <string>
+
+#include "base/inifile.hh"
+#include "base/output.hh"
+#include "mem/mem_object.hh"
+#include "mem/port.hh"
+#include "sim/builder.hh"
+#include "sim/sim_object.hh"
+
+using namespace std;
+
+/**
+ * Look up a MemObject port. Helper function for connectPorts().
+ */
+Port *
+lookupPort(SimObject *so, const std::string &name, int i)
+{
+ MemObject *mo = dynamic_cast<MemObject *>(so);
+ if (mo == NULL) {
+ warn("error casting SimObject %s to MemObject", so->name());
+ return NULL;
+ }
+
+ Port *p = mo->getPort(name, i);
+ if (p == NULL)
+ warn("error looking up port %s on object %s", name, so->name());
+ return p;
+}
+
+
+/**
+ * Connect the described MemObject ports. Called from Python via SWIG.
+ */
+int
+connectPorts(SimObject *o1, const std::string &name1, int i1,
+ SimObject *o2, const std::string &name2, int i2)
+{
+ Port *p1 = lookupPort(o1, name1, i1);
+ Port *p2 = lookupPort(o2, name2, i2);
+
+ if (p1 == NULL || p2 == NULL) {
+ warn("connectPorts: port lookup error");
+ return 0;
+ }
+
+ p1->setPeer(p2);
+ p2->setPeer(p1);
+
+ return 1;
+}
+
+inline IniFile &
+inifile()
+{
+ static IniFile inifile;
+ return inifile;
+}
+
+SimObject *
+createSimObject(const string &name)
+{
+ return SimObjectClass::createObject(inifile(), name);
+}
+
+/**
+ * Pointer to the Python function that maps names to SimObjects.
+ */
+PyObject *resolveFunc = NULL;
+
+/**
+ * Convert a pointer to the Python object that SWIG wraps around a C++
+ * SimObject pointer back to the actual C++ pointer. See main.i.
+ */
+extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
+
+SimObject *
+resolveSimObject(const string &name)
+{
+ PyObject *pyPtr = PyEval_CallFunction(resolveFunc, "(s)", name.c_str());
+ if (pyPtr == NULL) {
+ PyErr_Print();
+ panic("resolveSimObject: failure on call to Python for %s", name);
+ }
+
+ SimObject *simObj = convertSwigSimObjectPtr(pyPtr);
+ if (simObj == NULL)
+ panic("resolveSimObject: failure on pointer conversion for %s", name);
+
+ return simObj;
+}
+
+/**
+ * Load config.ini into C++ database. Exported to Python via SWIG;
+ * invoked from m5.instantiate().
+ */
+void
+loadIniFile(PyObject *_resolveFunc)
+{
+ resolveFunc = _resolveFunc;
+ configStream = simout.find("config.out");
+
+ // The configuration database is now complete; start processing it.
+ inifile().load(simout.resolve("config.ini"));
+}
+
diff --git a/src/python/swig/pyobject.hh b/src/python/swig/pyobject.hh
new file mode 100644
index 000000000..d8efc9149
--- /dev/null
+++ b/src/python/swig/pyobject.hh
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+#include <Python.h>
+
+#include "cpu/base.hh"
+#include "sim/host.hh"
+#include "sim/serialize.hh"
+#include "sim/sim_object.hh"
+#include "sim/system.hh"
+
+SimObject *createSimObject(const std::string &name);
+extern "C" SimObject *convertSwigSimObjectPtr(PyObject *);
+SimObject *resolveSimObject(const std::string &name);
+void loadIniFile(PyObject *_resolveFunc);
+
+
+/**
+ * Connect the described MemObject ports. Called from Python via SWIG.
+ */
+int connectPorts(SimObject *o1, const std::string &name1, int i1,
+ SimObject *o2, const std::string &name2, int i2);
+
+inline BaseCPU *
+convertToBaseCPUPtr(SimObject *obj)
+{
+ BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj);
+
+ if (ptr == NULL)
+ warn("Casting to BaseCPU pointer failed");
+ return ptr;
+}
+
+inline System *
+convertToSystemPtr(SimObject *obj)
+{
+ System *ptr = dynamic_cast<System *>(obj);
+
+ if (ptr == NULL)
+ warn("Casting to System pointer failed");
+ return ptr;
+}
+
+inline void
+initAll()
+{
+ SimObject::initAll();
+}
+
+inline void
+regAllStats()
+{
+ SimObject::regAllStats();
+}
+
+inline void
+serializeAll(const std::string &cpt_dir)
+{
+ Serializable::serializeAll(cpt_dir);
+}
+
+inline void
+unserializeAll(const std::string &cpt_dir)
+{
+ Serializable::unserializeAll(cpt_dir);
+}
+
diff --git a/src/python/swig/random.i b/src/python/swig/random.i
new file mode 100644
index 000000000..657a59780
--- /dev/null
+++ b/src/python/swig/random.i
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%module random
+
+%include "stdint.i"
+
+%{
+#include <cstdlib>
+
+#include "sim/host.hh"
+
+inline void
+seed(uint64_t seed)
+{
+ ::srand48(seed & ULL(0xffffffffffff));
+}
+%}
+
+%inline %{
+extern void seed(uint64_t seed);
+%}
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._random"
+%}
diff --git a/src/python/swig/sim_object.i b/src/python/swig/sim_object.i
new file mode 100644
index 000000000..b2af72c61
--- /dev/null
+++ b/src/python/swig/sim_object.i
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%module sim_object
+
+%{
+#include "python/swig/pyobject.hh"
+%}
+
+// import these files for SWIG to wrap
+%include "stdint.i"
+%include "std_string.i"
+%include "sim/host.hh"
+
+class BaseCPU;
+
+class SimObject {
+ public:
+ enum State {
+ Running,
+ Draining,
+ Drained
+ };
+
+ enum MemoryMode {
+ Invalid,
+ Atomic,
+ Timing
+ };
+
+ unsigned int drain(Event *drain_event);
+ void resume();
+ void switchOut();
+ void takeOverFrom(BaseCPU *cpu);
+ SimObject(const std::string &_name);
+};
+
+class System {
+ private:
+ System();
+ public:
+ void setMemoryMode(SimObject::MemoryMode mode);
+};
+
+SimObject *createSimObject(const std::string &name);
+
+int connectPorts(SimObject *o1, const std::string &name1, int i1,
+ SimObject *o2, const std::string &name2, int i2);
+
+BaseCPU *convertToBaseCPUPtr(SimObject *obj);
+System *convertToSystemPtr(SimObject *obj);
+
+void serializeAll(const std::string &cpt_dir);
+void unserializeAll(const std::string &cpt_dir);
+
+void initAll();
+void regAllStats();
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._sim_object"
+
+// Convert a pointer to the Python object that SWIG wraps around a
+// C++ SimObject pointer back to the actual C++ pointer.
+SimObject *
+convertSwigSimObjectPtr(PyObject *pyObj)
+{
+ SimObject *so;
+ if (SWIG_ConvertPtr(pyObj, (void **) &so, SWIGTYPE_p_SimObject, 0) == -1)
+ return NULL;
+ return so;
+}
+%}
diff --git a/src/python/swig/stats.i b/src/python/swig/stats.i
new file mode 100644
index 000000000..d36f82dbc
--- /dev/null
+++ b/src/python/swig/stats.i
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%module stats
+
+%include "std_string.i"
+
+%{
+#include "base/statistics.hh"
+#include "base/stats/mysql.hh"
+#include "base/stats/text.hh"
+#include "sim/stat_control.hh"
+%}
+
+namespace Stats {
+void initSimStats();
+void initText(const std::string &filename, bool desc=true, bool compat=true);
+void initMySQL(std::string host, std::string database, std::string user,
+ std::string passwd, std::string project, std::string name,
+ std::string sample);
+
+void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0);
+
+void check();
+void dump();
+void reset();
+
+/* namespace Stat */ }
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._stats"
+%}
diff --git a/src/python/swig/trace.i b/src/python/swig/trace.i
new file mode 100644
index 000000000..69b44c025
--- /dev/null
+++ b/src/python/swig/trace.i
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Nathan Binkert
+ */
+
+%module trace
+
+%{
+#include "base/trace.hh"
+#include "sim/host.hh"
+
+inline void
+output(const char *filename)
+{
+ Trace::setOutput(filename);
+}
+
+inline void
+set(const char *flag)
+{
+ Trace::changeFlag(flag, true);
+}
+
+inline void
+clear(const char *flag)
+{
+ Trace::changeFlag(flag, false);
+}
+
+inline void
+ignore(const char *expr)
+{
+ Trace::ignore.setExpression(expr);
+}
+
+using Trace::enabled;
+%}
+
+%inline %{
+extern void output(const char *string);
+extern void set(const char *string);
+extern void clear(const char *string);
+extern void ignore(const char *expr);
+extern bool enabled;
+%}
+
+%wrapper %{
+// fix up module name to reflect the fact that it's inside the m5 package
+#undef SWIG_name
+#define SWIG_name "m5.internal._trace"
+%}
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-18 14:34:34 +0000