diff options
Diffstat (limited to 'src/python')
-rw-r--r-- | src/python/m5/objects/BaseCPU.py | 3 | ||||
-rw-r--r-- | src/python/m5/objects/O3CPU.py | 2 | ||||
-rw-r--r-- | src/python/m5/objects/OzoneCPU.py | 4 | ||||
-rw-r--r-- | src/python/m5/objects/Root.py | 1 | ||||
-rw-r--r-- | src/python/m5/objects/System.py | 1 |
5 files changed, 11 insertions, 0 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 3dd0bda01..05ccbca6a 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -26,6 +26,9 @@ class BaseCPU(SimObject): "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") + stats_reset_inst = Param.Counter(0, + "reset stats once this many instructions are committed") + progress_interval = Param.Tick(0, "interval to print out the progress message") defer_registration = Param.Bool(False, "defer registration with system (for sampling)") diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 5100c7ccb..59b40c6e8 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -9,6 +9,8 @@ class DerivO3CPU(BaseCPU): activity = Param.Unsigned(0, "Initial count") numThreads = Param.Unsigned(1, "number of HW thread contexts") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") if build_env['USE_CHECKER']: if not build_env['FULL_SYSTEM']: checker = Param.BaseCPU(O3Checker(workload=Parent.workload, diff --git a/src/python/m5/objects/OzoneCPU.py b/src/python/m5/objects/OzoneCPU.py index 8f25d77ed..0913e044c 100644 --- a/src/python/m5/objects/OzoneCPU.py +++ b/src/python/m5/objects/OzoneCPU.py @@ -8,12 +8,15 @@ class DerivOzoneCPU(BaseCPU): numThreads = Param.Unsigned("number of HW thread contexts") checker = Param.BaseCPU("Checker CPU") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") icache_port = Port("Instruction Port") dcache_port = Port("Data Port") width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") + frontEndLatency = Param.Unsigned("Front end latency") backEndWidth = Param.Unsigned("Back end width") backEndSquashLatency = Param.Unsigned("Back end squash latency") backEndLatency = Param.Unsigned("Back end latency") @@ -76,6 +79,7 @@ class DerivOzoneCPU(BaseCPU): LQEntries = Param.Unsigned("Number of load queue entries") SQEntries = Param.Unsigned("Number of store queue entries") + lsqLimits = Param.Bool(True, "LSQ size limits dispatch") LFSTSize = Param.Unsigned("Last fetched store table size") SSITSize = Param.Unsigned("Store set ID table size") diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py index f01fc06c4..8e8d87f6d 100644 --- a/src/python/m5/objects/Root.py +++ b/src/python/m5/objects/Root.py @@ -1,6 +1,7 @@ from m5.SimObject import SimObject from m5.params import * from Serialize import Serialize +from Serialize import Statreset from Statistics import Statistics from Trace import Trace from ExeTrace import ExecutionTrace diff --git a/src/python/m5/objects/System.py b/src/python/m5/objects/System.py index bc2a002cb..e7dd1bc60 100644 --- a/src/python/m5/objects/System.py +++ b/src/python/m5/objects/System.py @@ -16,6 +16,7 @@ class System(SimObject): boot_osflags = Param.String("a", "boot flags to pass to the kernel") kernel = Param.String("file that contains the kernel code") readfile = Param.String("", "file to read startup script from") + symbolfile = Param.String("", "file to get the symbols from") class AlphaSystem(System): type = 'AlphaSystem' |