diff options
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/SConscript | 13 | ||||
| -rw-r--r-- | src/python/m5/objects/Ethernet.py | 9 | ||||
| -rw-r--r-- | src/python/m5/objects/O3CPU.py | 5 |
3 files changed, 22 insertions, 5 deletions
diff --git a/src/python/SConscript b/src/python/SConscript index 94db1a747..6662c8a45 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -29,14 +29,14 @@ # Authors: Steve Reinhardt # Nathan Binkert -import os, os.path, re, sys -from zipfile import PyZipFile +import os +import zipfile # handy function for path joins def join(*args): return os.path.normpath(os.path.join(*args)) -Import('env') +Import('*') # This SConscript is in charge of collecting .py files and generating # a zip archive that is appended to the m5 binary. @@ -106,6 +106,11 @@ def swig_it(module): '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES') swig_modules.append(module) + Source('swig/%s_wrap.cc' % module) + +Source('swig/init.cc') +Source('swig/pyevent.cc') +Source('swig/pyobject.cc') swig_it('core') swig_it('debug') @@ -144,7 +149,7 @@ env.Command('swig/init.cc', swig_cc_files, MakeSwigInit) # Action function to build the zip archive. Uses the PyZipFile module # included in the standard Python library. def buildPyZip(target, source, env): - pzf = PyZipFile(str(target[0]), 'w') + pzf = zipfile.PyZipFile(str(target[0]), 'w') for s in source: pzf.writepy(str(s)) diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py index a52e35511..bfe30950c 100644 --- a/src/python/m5/objects/Ethernet.py +++ b/src/python/m5/objects/Ethernet.py @@ -67,7 +67,14 @@ if build_env['ALPHA_TLASER']: class IGbE(PciDevice): type = 'IGbE' - hardware_address = Param.EthernetAddr(NextEthernetAddr, "Ethernet Hardware Address") + hardware_address = Param.String("Ethernet Hardware Address") + use_flow_control = Param.Bool(False, "Should we use xon/xoff flow contorl (UNIMPLMENTD)") + rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") + tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") + rx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") + tx_desc_cache_size = Param.Int(64, "Number of enteries in the rx descriptor cache") + clock = Param.Clock('500MHz', "Clock speed of the device") + class IGbEPciData(PciConfigData): VendorID = 0x8086 diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py index 20eef383f..5fba4e96f 100644 --- a/src/python/m5/objects/O3CPU.py +++ b/src/python/m5/objects/O3CPU.py @@ -116,3 +116,8 @@ class DerivO3CPU(BaseCPU): smtROBPolicy = Param.String("SMT ROB Sharing Policy") smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") smtCommitPolicy = Param.String("SMT Commit Policy") + + def addPrivateSplitL1Caches(self, ic, dc): + BaseCPU.addPrivateSplitL1Caches(self, ic, dc) + self.icache.tgts_per_mshr = 20 + self.dcache.tgts_per_mshr = 20 |