diff options
Diffstat (limited to 'src/python')
| -rw-r--r-- | src/python/SConscript | 195 | ||||
| -rw-r--r-- | src/python/m5/internal/__init__.py | 35 | ||||
| -rw-r--r-- | src/python/m5/objects/BaseCache.py | 3 | ||||
| -rw-r--r-- | src/python/m5/objects/Bridge.py | 9 | ||||
| -rw-r--r-- | src/python/m5/objects/Bus.py | 1 | ||||
| -rw-r--r-- | src/python/m5/objects/Device.py | 6 | ||||
| -rw-r--r-- | src/python/m5/params.py | 27 |
7 files changed, 136 insertions, 140 deletions
diff --git a/src/python/SConscript b/src/python/SConscript index 6662c8a45..562278aa0 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -30,129 +30,84 @@ # Nathan Binkert import os -import zipfile - -# handy function for path joins -def join(*args): - return os.path.normpath(os.path.join(*args)) - Import('*') -# This SConscript is in charge of collecting .py files and generating -# a zip archive that is appended to the m5 binary. - -# List of files & directories to include in the zip file. To include -# a package, list only the root directory of the package, not any -# internal .py files (else they will get the path stripped off when -# they are imported into the zip file). -pyzip_files = [] - -# List of additional files on which the zip archive depends, but which -# are not included in pyzip_files... i.e. individual .py files within -# a package. -pyzip_dep_files = [] - -# Add the specified package to the zip archive. Adds the directory to -# pyzip_files and all included .py files to pyzip_dep_files. -def addPkg(pkgdir): - pyzip_files.append(pkgdir) - origdir = os.getcwd() - srcdir = join(Dir('.').srcnode().abspath, pkgdir) - os.chdir(srcdir) - for path, dirs, files in os.walk('.'): - for i,dir in enumerate(dirs): - if dir == 'SCCS': - del dirs[i] - break - - for f in files: - if f.endswith('.py'): - pyzip_dep_files.append(join(pkgdir, path, f)) - - os.chdir(origdir) - -# Generate Python file that contains a dict specifying the current -# build_env flags. -def MakeDefinesPyFile(target, source, env): - f = file(str(target[0]), 'w') - print >>f, "m5_build_env = ", source[0] - f.close() - -optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions]) -env.Command('m5/defines.py', Value(optionDict), MakeDefinesPyFile) - -def MakeInfoPyFile(target, source, env): - f = file(str(target[0]), 'w') - for src in source: - data = ''.join(file(src.srcnode().abspath, 'r').xreadlines()) - print >>f, "%s = %s" % (src, repr(data)) - f.close() - -env.Command('m5/info.py', - [ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ], - MakeInfoPyFile) - -# Now specify the packages & files for the zip archive. -addPkg('m5') -pyzip_files.append('m5/defines.py') -pyzip_files.append('m5/info.py') -pyzip_files.append(join(env['ROOT'], 'util/pbs/jobfile.py')) -pyzip_files.append(join(env['ROOT'], 'src/base/traceflags.py')) - -swig_modules = [] -def swig_it(module): - env.Command(['swig/%s_wrap.cc' % module, 'm5/internal/%s.py' % module], - 'swig/%s.i' % module, - '$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' - '-o ${TARGETS[0]} $SOURCES') - swig_modules.append(module) - Source('swig/%s_wrap.cc' % module) - Source('swig/init.cc') Source('swig/pyevent.cc') Source('swig/pyobject.cc') -swig_it('core') -swig_it('debug') -swig_it('event') -swig_it('random') -swig_it('sim_object') -swig_it('stats') -swig_it('trace') - -# Automatically generate m5/internals/__init__.py -def MakeInternalsInit(target, source, env): - f = file(str(target[0]), 'w') - for m in swig_modules: - print >>f, 'import %s' % m - f.close() - -swig_py_files = [ 'm5/internal/%s.py' % m for m in swig_modules ] -env.Command('m5/internal/__init__.py', swig_py_files, MakeInternalsInit) -pyzip_dep_files.append('m5/internal/__init__.py') - -def MakeSwigInit(target, source, env): - f = file(str(target[0]), 'w') - print >>f, 'extern "C" {' - for m in swig_modules: - print >>f, ' void init_%s();' % m - print >>f, '}' - print >>f, 'void init_swig() {' - for m in swig_modules: - print >>f, ' init_%s();' % m - print >>f, '}' - f.close() - -swig_cc_files = [ 'swig/%s_wrap.cc' % m for m in swig_modules ] -env.Command('swig/init.cc', swig_cc_files, MakeSwigInit) - -# Action function to build the zip archive. Uses the PyZipFile module -# included in the standard Python library. -def buildPyZip(target, source, env): - pzf = zipfile.PyZipFile(str(target[0]), 'w') - for s in source: - pzf.writepy(str(s)) - -# Add the zip file target to the environment. -env.Command('m5py.zip', pyzip_files, buildPyZip) -env.Depends('m5py.zip', pyzip_dep_files) +PySource('m5', 'm5/__init__.py') +PySource('m5', 'm5/SimObject.py') +PySource('m5', 'm5/attrdict.py') +PySource('m5', 'm5/convert.py') +PySource('m5', 'm5/event.py') +PySource('m5', 'm5/main.py') +PySource('m5', 'm5/multidict.py') +PySource('m5', 'm5/params.py') +PySource('m5', 'm5/proxy.py') +PySource('m5', 'm5/smartdict.py') +PySource('m5', 'm5/stats.py') +PySource('m5', 'm5/ticks.py') +PySource('m5', 'm5/util.py') + +PySource('m5', os.path.join(env['ROOT'], 'util/pbs/jobfile.py')) + +SwigSource('m5.internal', 'swig/core.i') +SwigSource('m5.internal', 'swig/debug.i') +SwigSource('m5.internal', 'swig/event.i') +SwigSource('m5.internal', 'swig/random.i') +SwigSource('m5.internal', 'swig/sim_object.i') +SwigSource('m5.internal', 'swig/stats.i') +SwigSource('m5.internal', 'swig/trace.i') +PySource('m5.internal', 'm5/internal/__init__.py') + +SimObject('m5/objects/AlphaConsole.py') +SimObject('m5/objects/AlphaTLB.py') +SimObject('m5/objects/BadDevice.py') +SimObject('m5/objects/BaseCPU.py') +SimObject('m5/objects/BaseCache.py') +SimObject('m5/objects/BaseHier.py') +SimObject('m5/objects/BaseMem.py') +SimObject('m5/objects/BaseMemory.py') +SimObject('m5/objects/BranchPred.py') +SimObject('m5/objects/Bridge.py') +SimObject('m5/objects/Bus.py') +SimObject('m5/objects/Checker.py') +SimObject('m5/objects/CoherenceProtocol.py') +SimObject('m5/objects/DRAMMemory.py') +SimObject('m5/objects/Device.py') +SimObject('m5/objects/DiskImage.py') +SimObject('m5/objects/Ethernet.py') +SimObject('m5/objects/FUPool.py') +SimObject('m5/objects/FastCPU.py') +#SimObject('m5/objects/FreebsdSystem.py') +SimObject('m5/objects/FuncUnit.py') +SimObject('m5/objects/FuncUnitConfig.py') +SimObject('m5/objects/FunctionalMemory.py') +SimObject('m5/objects/HierParams.py') +SimObject('m5/objects/Ide.py') +SimObject('m5/objects/IntrControl.py') +SimObject('m5/objects/LinuxSystem.py') +SimObject('m5/objects/MainMemory.py') +SimObject('m5/objects/MemObject.py') +SimObject('m5/objects/MemTest.py') +SimObject('m5/objects/MemoryController.py') +SimObject('m5/objects/O3CPU.py') +SimObject('m5/objects/OzoneCPU.py') +SimObject('m5/objects/Pci.py') +SimObject('m5/objects/PhysicalMemory.py') +SimObject('m5/objects/Platform.py') +SimObject('m5/objects/Process.py') +SimObject('m5/objects/Repl.py') +SimObject('m5/objects/Root.py') +SimObject('m5/objects/Sampler.py') +SimObject('m5/objects/SimConsole.py') +SimObject('m5/objects/SimpleCPU.py') +SimObject('m5/objects/SimpleDisk.py') +#SimObject('m5/objects/SimpleOzoneCPU.py') +SimObject('m5/objects/SparcTLB.py') +SimObject('m5/objects/System.py') +SimObject('m5/objects/T1000.py') +#SimObject('m5/objects/Tru64System.py') +SimObject('m5/objects/Tsunami.py') +SimObject('m5/objects/Uart.py') diff --git a/src/python/m5/internal/__init__.py b/src/python/m5/internal/__init__.py new file mode 100644 index 000000000..6b7859cd7 --- /dev/null +++ b/src/python/m5/internal/__init__.py @@ -0,0 +1,35 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Nathan Binkert + +import core +import debug +import event +import random +import sim_object +import stats +import trace diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index ee8e76bff..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,7 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") + fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") + fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py index 8226fe8d2..48dbbe307 100644 --- a/src/python/m5/objects/Bus.py +++ b/src/python/m5/objects/Bus.py @@ -11,6 +11,7 @@ class Bus(MemObject): clock = Param.Clock("1GHz", "bus clock speed") width = Param.Int(64, "bus width (bytes)") responder_set = Param.Bool(False, "Did the user specify a default responder.") + block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") if build_env['FULL_SYSTEM']: responder = BadAddr(pio_addr=0x0, pio_latency="1ps") default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' diff --git a/src/python/m5/params.py b/src/python/m5/params.py index 9892df97c..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -51,6 +51,7 @@ import sys import time import convert +import proxy import ticks from util import * @@ -347,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' @@ -477,12 +478,13 @@ def IncEthernetAddr(addr, val = 1): assert(bytes[0] <= 255) return ':'.join(map(lambda x: '%02x' % x, bytes)) -class NextEthernetAddr(object): - addr = "00:90:00:00:00:01" +_NextEthernetAddr = "00:90:00:00:00:01" +def NextEthernetAddr(): + global _NextEthernetAddr - def __init__(self, inc = 1): - self.value = NextEthernetAddr.addr - NextEthernetAddr.addr = IncEthernetAddr(NextEthernetAddr.addr, inc) + value = _NextEthernetAddr + _NextEthernetAddr = IncEthernetAddr(_NextEthernetAddr, 1) + return value class EthernetAddr(ParamValue): cxx_type = 'Net::EthAddr' @@ -508,17 +510,11 @@ class EthernetAddr(ParamValue): def unproxy(self, base): if self.value == NextEthernetAddr: - self.addr = self.value().value + return EthernetAddr(self.value()) return self - def __str__(self): - if self.value == NextEthernetAddr: - if hasattr(self, 'addr'): - return self.addr - else: - return "NextEthernetAddr (unresolved)" - else: - return self.value + def ini_str(self): + return self.value time_formats = [ "%a %b %d %H:%M:%S %Z %Y", "%a %b %d %H:%M:%S %Z %Y", @@ -1028,6 +1024,5 @@ __all__ = ['Param', 'VectorParam', # see comment on imports at end of __init__.py. from SimObject import isSimObject, isSimObjectSequence, isSimObjectClass -import proxy import objects import internal |