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-rw-r--r--src/python/m5/__init__.py7
-rw-r--r--src/python/m5/main.py3
-rw-r--r--src/python/m5/objects/BaseCPU.py2
-rw-r--r--src/python/m5/objects/Tsunami.py1
4 files changed, 9 insertions, 4 deletions
diff --git a/src/python/m5/__init__.py b/src/python/m5/__init__.py
index d41fd5a61..579562b38 100644
--- a/src/python/m5/__init__.py
+++ b/src/python/m5/__init__.py
@@ -39,6 +39,9 @@ from cc_main import simulate, SimLoopExitEvent
# import the m5 compile options
import defines
+# define a MaxTick parameter
+MaxTick = 2**63 - 1
+
# define this here so we can use it right away if necessary
def panic(string):
print >>sys.stderr, 'panic:', string
@@ -171,10 +174,10 @@ def switchCpus(cpuList):
for cpu in old_cpus:
if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU", cpu
+ raise TypeError, "%s is not of type BaseCPU" % cpu
for cpu in new_cpus:
if not isinstance(cpu, objects.BaseCPU):
- raise TypeError, "%s is not of type BaseCPU", cpu
+ raise TypeError, "%s is not of type BaseCPU" % cpu
# Drain all of the individual CPUs
drain_event = cc_main.createCountedDrain()
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index ccd6c5807..ef37f62ac 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -181,6 +181,8 @@ bool_option("print-cpseq", default=False,
help="Print correct path sequence numbers in trace output")
#bool_option("print-reg-delta", default=False,
# help="Print which registers changed to what in trace output")
+bool_option("legion-lock", default=False,
+ help="Compare simulator state with Legion simulator every cycle")
options = attrdict()
arguments = []
@@ -296,6 +298,7 @@ def main():
objects.ExecutionTrace.print_fetchseq = options.print_fetch_seq
objects.ExecutionTrace.print_cpseq = options.print_cpseq
#objects.ExecutionTrace.print_reg_delta = options.print_reg_delta
+ objects.ExecutionTrace.legion_lockstep = options.legion_lock
sys.argv = arguments
sys.path = [ os.path.dirname(sys.argv[0]) ] + sys.path
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index b6dc08e46..4e34e8a4e 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -8,7 +8,6 @@ from Bus import Bus
class BaseCPU(SimObject):
type = 'BaseCPU'
abstract = True
- mem = Param.MemObject("memory")
system = Param.System(Parent.any, "system object")
cpu_id = Param.Int("CPU identifier")
@@ -47,7 +46,6 @@ class BaseCPU(SimObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
-# self.mem = dc
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 78ab65b31..ffe93727b 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -76,6 +76,7 @@ class Tsunami(Platform):
self.pchip.pio = bus.port
self.pciconfig.pio = bus.default
bus.responder_set = True
+ bus.responder = self.pciconfig
self.fake_sm_chip.pio = bus.port
self.fake_uart1.pio = bus.port
self.fake_uart2.pio = bus.port