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-rw-r--r--src/python/m5/objects/BaseCPU.py3
-rw-r--r--src/python/m5/objects/Bus.py2
-rw-r--r--src/python/m5/objects/FUPool.py6
-rw-r--r--src/python/m5/objects/FuncUnitConfig.py41
-rw-r--r--src/python/m5/objects/MemTest.py11
-rw-r--r--src/python/m5/objects/O3CPU.py11
-rw-r--r--src/python/m5/objects/PhysicalMemory.py1
-rw-r--r--src/python/m5/params.py2
-rw-r--r--src/python/m5/proxy.py17
9 files changed, 80 insertions, 14 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 0b887cceb..b6dc08e46 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -11,10 +11,11 @@ class BaseCPU(SimObject):
mem = Param.MemObject("memory")
system = Param.System(Parent.any, "system object")
+ cpu_id = Param.Int("CPU identifier")
+
if build_env['FULL_SYSTEM']:
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
- cpu_id = Param.Int(-1, "CPU identifier")
else:
workload = VectorParam.Process("processes to run")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index f6828a0d5..6710111e5 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -6,3 +6,5 @@ class Bus(MemObject):
port = VectorPort("vector port for connecting devices")
default = Port("Default port for requests that aren't handeled by a device.")
bus_id = Param.Int(0, "blah")
+ clock = Param.Clock("1GHz", "bus clock speed")
+ width = Param.Int(64, "bus width (bytes)")
diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index 4b4be79a6..916183bd7 100644
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,6 +1,12 @@
from m5.SimObject import SimObject
from m5.params import *
+from FuncUnit import *
+from FuncUnitConfig import *
class FUPool(SimObject):
type = 'FUPool'
FUList = VectorParam.FUDesc("list of FU's for this pool")
+
+class DefaultFUPool(FUPool):
+ FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+ WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
new file mode 100644
index 000000000..43d7a4bb7
--- /dev/null
+++ b/src/python/m5/objects/FuncUnitConfig.py
@@ -0,0 +1,41 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+ opList = [ OpDesc(opClass='IntAlu') ]
+ count = 6
+
+class IntMultDiv(FUDesc):
+ opList = [ OpDesc(opClass='IntMult', opLat=3),
+ OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+ count=2
+
+class FP_ALU(FUDesc):
+ opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+ OpDesc(opClass='FloatCmp', opLat=2),
+ OpDesc(opClass='FloatCvt', opLat=2) ]
+ count = 4
+
+class FP_MultDiv(FUDesc):
+ opList = [ OpDesc(opClass='FloatMult', opLat=4),
+ OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+ OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+ count = 2
+
+class ReadPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead') ]
+ count = 0
+
+class WritePort(FUDesc):
+ opList = [ OpDesc(opClass='MemWrite') ]
+ count = 0
+
+class RdWrPort(FUDesc):
+ opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+ count = 4
+
+class IprPort(FUDesc):
+ opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+ count = 1
+
diff --git a/src/python/m5/objects/MemTest.py b/src/python/m5/objects/MemTest.py
index 97600768f..83399be80 100644
--- a/src/python/m5/objects/MemTest.py
+++ b/src/python/m5/objects/MemTest.py
@@ -1,13 +1,13 @@
from m5.SimObject import SimObject
from m5.params import *
+from m5.proxy import *
+from m5 import build_env
+
class MemTest(SimObject):
type = 'MemTest'
- cache = Param.BaseCache("L1 cache")
- check_mem = Param.FunctionalMemory("check memory")
- main_mem = Param.FunctionalMemory("hierarchical memory")
max_loads = Param.Counter("number of loads to execute")
+ atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
memory_size = Param.Int(65536, "memory size")
- percent_copies = Param.Percent(0, "target copy percentage")
percent_dest_unaligned = Param.Percent(50,
"percent of copy dest address that are unaligned")
percent_reads = Param.Percent(65, "target read percentage")
@@ -18,3 +18,6 @@ class MemTest(SimObject):
progress_interval = Param.Counter(1000000,
"progress report interval (in accesses)")
trace_addr = Param.Addr(0, "address to trace")
+
+ test = Port("Port to the memory system to test")
+ functional = Port("Port to the functional memory used for verification")
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 59b40c6e8..20eef383f 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -3,6 +3,7 @@ from m5.proxy import *
from m5 import build_env
from BaseCPU import BaseCPU
from Checker import O3Checker
+from FUPool import *
class DerivO3CPU(BaseCPU):
type = 'DerivO3CPU'
@@ -14,11 +15,13 @@ class DerivO3CPU(BaseCPU):
if build_env['USE_CHECKER']:
if not build_env['FULL_SYSTEM']:
checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
- exitOnError=True,
+ exitOnError=False,
+ updateOnError=True,
warnOnlyOnLoadError=False),
"checker")
else:
- checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
+ checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
+ warnOnlyOnLoadError=False), "checker")
checker.itb = Parent.itb
checker.dtb = Parent.dtb
@@ -57,7 +60,7 @@ class DerivO3CPU(BaseCPU):
issueWidth = Param.Unsigned(8, "Issue width")
wbWidth = Param.Unsigned(8, "Writeback width")
wbDepth = Param.Unsigned(1, "Writeback depth")
- fuPool = Param.FUPool("Functional Unit pool")
+ fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
"delay")
@@ -77,7 +80,7 @@ class DerivO3CPU(BaseCPU):
localHistoryBits = Param.Unsigned(11, "Bits for the local history")
globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
globalCtrBits = Param.Unsigned(2, "Bits per counter")
- globalHistoryBits = Param.Unsigned(4096, "Bits of history")
+ globalHistoryBits = Param.Unsigned(13, "Bits of history")
choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
diff --git a/src/python/m5/objects/PhysicalMemory.py b/src/python/m5/objects/PhysicalMemory.py
index dd3ffd651..4e097543d 100644
--- a/src/python/m5/objects/PhysicalMemory.py
+++ b/src/python/m5/objects/PhysicalMemory.py
@@ -5,6 +5,7 @@ from MemObject import *
class PhysicalMemory(MemObject):
type = 'PhysicalMemory'
port = Port("the access port")
+ functional = Port("Functional Access Port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
latency = Param.Latency(Parent.clock, "latency of an access")
diff --git a/src/python/m5/params.py b/src/python/m5/params.py
index cbbd23004..93d784181 100644
--- a/src/python/m5/params.py
+++ b/src/python/m5/params.py
@@ -804,7 +804,7 @@ class PortRef(object):
newRef.simobj = simobj
assert(isSimObject(newRef.simobj))
if self.peer and not proxy.isproxy(self.peer):
- peerObj = memo[self.peer.simobj]
+ peerObj = self.peer.simobj(_memo=memo)
newRef.peer = self.peer.clone(peerObj, memo)
assert(not isinstance(newRef.peer, VectorPortRef))
return newRef
diff --git a/src/python/m5/proxy.py b/src/python/m5/proxy.py
index 7ebc0ae19..e539f14ee 100644
--- a/src/python/m5/proxy.py
+++ b/src/python/m5/proxy.py
@@ -33,6 +33,8 @@
#
#####################################################################
+import copy
+
class BaseProxy(object):
def __init__(self, search_self, search_up):
self._search_self = search_self
@@ -129,15 +131,22 @@ class AttrProxy(BaseProxy):
return super(AttrProxy, self).__getattr__(self, attr)
if hasattr(self, '_pdesc'):
raise AttributeError, "Attribute reference on bound proxy"
- self._modifiers.append(attr)
- return self
+ # Return a copy of self rather than modifying self in place
+ # since self could be an indirect reference via a variable or
+ # parameter
+ new_self = copy.deepcopy(self)
+ new_self._modifiers.append(attr)
+ return new_self
# support indexing on proxies (e.g., Self.cpu[0])
def __getitem__(self, key):
if not isinstance(key, int):
raise TypeError, "Proxy object requires integer index"
- self._modifiers.append(key)
- return self
+ if hasattr(self, '_pdesc'):
+ raise AttributeError, "Index operation on bound proxy"
+ new_self = copy.deepcopy(self)
+ new_self._modifiers.append(key)
+ return new_self
def find(self, obj):
try:
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 04:10:56 +0000