2 files changed, 27 insertions, 2 deletions
diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py
index 5bf98be9c..4144397a6 100644
--- a/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@ -1,5 +1,7 @@
 from m5 import build_env
 from m5.config import *
+from AlphaTLB import AlphaDTB, AlphaITB
+from Bus import Bus
 
 class BaseCPU(SimObject):
     type = 'BaseCPU'
@@ -8,8 +10,8 @@ class BaseCPU(SimObject):
 
     system = Param.System(Parent.any, "system object")
     if build_env['FULL_SYSTEM']:
-        dtb = Param.AlphaDTB("Data TLB")
-        itb = Param.AlphaITB("Instruction TLB")
+        dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
+        itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
         cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
@@ -27,3 +29,25 @@ class BaseCPU(SimObject):
         "defer registration with system (for sampling)")
 
     clock = Param.Clock(Parent.clock, "clock speed")
+
+    _mem_ports = []
+
+    def connectMemPorts(self, bus):
+        for p in self._mem_ports:
+            exec('self.%s = bus.port' % p)
+
+    def addPrivateSplitL1Caches(self, ic, dc):
+        assert(len(self._mem_ports) == 2)
+        self.icache = ic
+        self.dcache = dc
+        self.icache_port = ic.cpu_side
+        self.dcache_port = dc.cpu_side
+        self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+
+    def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
+        self.addPrivateSplitL1Caches(ic, dc)
+        self.toL2Bus = Bus()
+        self.connectMemPorts(self.toL2Bus)
+        self.l2cache = l2c
+        self.l2cache.cpu_side = toL2Bus.port
+        self._mem_ports = ['l2cache.mem_side']
diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 41208929a..900bbf28c 100644
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -22,6 +22,7 @@ class DerivO3CPU(BaseCPU):
     cachePorts = Param.Unsigned("Cache Ports")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
+    _mem_ports = ['icache_port', 'dcache_port']
 
     decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
     renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")