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-rw-r--r--src/python/m5/objects/Bridge.py2
-rw-r--r--src/python/m5/objects/Bus.py1
2 files changed, 3 insertions, 0 deletions
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index ee8e76bff..e123c2891 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -9,3 +9,5 @@ class Bridge(MemObject):
queue_size_b = Param.Int(16, "The number of requests to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
write_ack = Param.Bool(False, "Should this bridge ack writes")
+ fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
+ fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/python/m5/objects/Bus.py b/src/python/m5/objects/Bus.py
index 8226fe8d2..48dbbe307 100644
--- a/src/python/m5/objects/Bus.py
+++ b/src/python/m5/objects/Bus.py
@@ -11,6 +11,7 @@ class Bus(MemObject):
clock = Param.Clock("1GHz", "bus clock speed")
width = Param.Int(64, "bus width (bytes)")
responder_set = Param.Bool(False, "Did the user specify a default responder.")
+ block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
if build_env['FULL_SYSTEM']:
responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")