summaryrefslogtreecommitdiff
path: root/src/python
diff options
context:
space:
mode:
Diffstat (limited to 'src/python')
-rw-r--r--src/python/m5/objects/SimConsole.py5
-rw-r--r--src/python/m5/objects/T1000.py6
2 files changed, 4 insertions, 7 deletions
diff --git a/src/python/m5/objects/SimConsole.py b/src/python/m5/objects/SimConsole.py
index bdd7f246d..dfad18eb6 100644
--- a/src/python/m5/objects/SimConsole.py
+++ b/src/python/m5/objects/SimConsole.py
@@ -1,14 +1,11 @@
from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
-class ConsoleListener(SimObject):
- type = 'ConsoleListener'
- port = Param.TcpPort(3456, "listen port")
class SimConsole(SimObject):
type = 'SimConsole'
append_name = Param.Bool(True, "append name() to filename")
intr_control = Param.IntrControl(Parent.any, "interrupt controller")
- listener = Param.ConsoleListener("console listener")
+ port = Param.TcpPort(3456, "listen port")
number = Param.Int(0, "console number")
output = Param.String('console', "file to dump output to")
diff --git a/src/python/m5/objects/T1000.py b/src/python/m5/objects/T1000.py
index 3ab6d4283..aeca491c4 100644
--- a/src/python/m5/objects/T1000.py
+++ b/src/python/m5/objects/T1000.py
@@ -3,7 +3,7 @@ from m5.proxy import *
from Device import BasicPioDevice, IsaFake, BadAddr
from Uart import Uart8250
from Platform import Platform
-from SimConsole import SimConsole, ConsoleListener
+from SimConsole import SimConsole
class MmDisk(BasicPioDevice):
@@ -69,11 +69,11 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!")
- hconsole = SimConsole(listener = ConsoleListener())
+ hconsole = SimConsole()
hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD()
- pconsole = SimConsole(listener = ConsoleListener())
+ pconsole = SimConsole()
puart0 = Uart8250(pio_addr=0x1f10000000)
# Attach I/O devices to specified bus object. Can't do this