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-rw-r--r--src/sim/BaseTLB.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/sim/BaseTLB.py b/src/sim/BaseTLB.py
index 9aca4a97c..8a03413a9 100644
--- a/src/sim/BaseTLB.py
+++ b/src/sim/BaseTLB.py
@@ -31,3 +31,4 @@ from m5.SimObject import SimObject
class BaseTLB(SimObject):
type = 'BaseTLB'
abstract = True
+ cxx_header = "sim/tlb.hh"