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Diffstat (limited to 'src/sim/ClockDomain.py')
| -rw-r--r-- | src/sim/ClockDomain.py | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/sim/ClockDomain.py b/src/sim/ClockDomain.py index 37958dc26..2a3b6addf 100644 --- a/src/sim/ClockDomain.py +++ b/src/sim/ClockDomain.py @@ -38,6 +38,7 @@ from m5.params import * from m5.SimObject import SimObject +from m5.proxy import * # Abstract clock domain class ClockDomain(SimObject): @@ -51,6 +52,9 @@ class SrcClockDomain(ClockDomain): cxx_header = "sim/clock_domain.hh" clock = Param.Clock("Clock period") + # A source clock must be associated with a voltage domain + voltage_domain = Param.VoltageDomain("Voltage domain") + # Derived clock domain with a parent clock domain and a frequency # divider class DerivedClockDomain(ClockDomain): |