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-rw-r--r--src/sim/Process.py7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/sim/Process.py b/src/sim/Process.py
index 743e5247c..2ffc51a33 100644
--- a/src/sim/Process.py
+++ b/src/sim/Process.py
@@ -26,13 +26,18 @@
#
# Authors: Nathan Binkert
-from m5.SimObject import SimObject
+from m5.SimObject import *
from m5.params import *
from m5.proxy import *
class Process(SimObject):
type = 'Process'
cxx_header = "sim/process.hh"
+
+ @cxxMethod
+ def map(self, vaddr, paddr, size, cacheable=False):
+ pass
+
input = Param.String('cin', "filename for stdin")
output = Param.String('cout', 'filename for stdout')
errout = Param.String('cerr', 'filename for stderr')