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-rw-r--r--src/sim/SConscript12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/sim/SConscript b/src/sim/SConscript
index 90d77848b..850af230e 100644
--- a/src/sim/SConscript
+++ b/src/sim/SConscript
@@ -33,9 +33,9 @@ Import('*')
SimObject('BaseTLB.py')
SimObject('ClockedObject.py')
SimObject('Root.py')
-SimObject('InstTracer.py')
SimObject('ClockDomain.py')
SimObject('VoltageDomain.py')
+SimObject('System.py')
Source('arguments.cc')
Source('async.cc')
@@ -51,19 +51,17 @@ Source('sim_events.cc')
Source('sim_object.cc')
Source('simulate.cc')
Source('stat_control.cc')
-Source('syscall_emul.cc')
Source('clock_domain.cc')
Source('voltage_domain.cc')
+Source('system.cc')
-if env['TARGET_ISA'] != 'no':
+if env['TARGET_ISA'] != 'null':
+ SimObject('InstTracer.py')
SimObject('Process.py')
- SimObject('System.py')
Source('faults.cc')
Source('process.cc')
Source('pseudo_inst.cc')
- Source('system.cc')
-
-if env['TARGET_ISA'] != 'no':
+ Source('syscall_emul.cc')
Source('tlb.cc')
DebugFlag('Checkpoint')