summaryrefslogtreecommitdiff
path: root/src/sim/System.py
diff options
context:
space:
mode:
Diffstat (limited to 'src/sim/System.py')
-rw-r--r--src/sim/System.py3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index 3caa907d7..d34a043c1 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -37,8 +37,9 @@ from PhysicalMemory import *
class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
-class System(SimObject):
+class System(MemObject):
type = 'System'
+ system_port = Port("System port")
@classmethod
def export_method_cxx_predecls(cls, code):