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Diffstat (limited to 'src/sim/System.py')
| -rw-r--r-- | src/sim/System.py | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 92883b299..3d45c23c0 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -39,6 +39,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] class System(MemObject): type = 'System' + cxx_header = "sim/system.hh" system_port = MasterPort("System port") # Override the clock from the ClockedObject which looks at the |