1 files changed, 7 insertions, 0 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index f680e64bf..88afea873 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -41,6 +41,13 @@ class System(MemObject):
     type = 'System'
     system_port = MasterPort("System port")
 
+    # Override the clock from the ClockedObject which looks at the
+    # parent clock by default
+    clock = '1t'
+    # @todo Either make this value 0 and treat it as an error if it is
+    # not overridden, or choose a more sensible value in the range of
+    # 1GHz
+
     @classmethod
     def export_method_cxx_predecls(cls, code):
         code('#include "sim/system.hh"')