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-rw-r--r--src/sim/System.py4
1 files changed, 0 insertions, 4 deletions
diff --git a/src/sim/System.py b/src/sim/System.py
index 8ebf7a024..f97096fcc 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -44,10 +44,6 @@ class System(MemObject):
system_port = MasterPort("System port")
@classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "sim/system.hh"')
-
- @classmethod
def export_methods(cls, code):
code('''
Enums::MemoryMode getMemoryMode() const;