summaryrefslogtreecommitdiff
path: root/src/sim
diff options
context:
space:
mode:
Diffstat (limited to 'src/sim')
-rw-r--r--src/sim/core.cc6
-rw-r--r--src/sim/core.hh6
-rw-r--r--src/sim/insttracer.hh2
-rw-r--r--src/sim/pseudo_inst.cc2
-rw-r--r--src/sim/pseudo_inst.hh2
-rw-r--r--src/sim/stat_control.cc2
-rw-r--r--src/sim/stat_control.hh2
7 files changed, 11 insertions, 11 deletions
diff --git a/src/sim/core.cc b/src/sim/core.cc
index 32642c8a4..1b7a034f0 100644
--- a/src/sim/core.cc
+++ b/src/sim/core.cc
@@ -55,7 +55,7 @@ double Hz;
double kHz;
double MHz;
double GHZ;
-/* namespace Float */ }
+} // namespace Float
namespace Int {
Tick s;
@@ -63,9 +63,9 @@ Tick ms;
Tick us;
Tick ns;
Tick ps;
-/* namespace Float */ }
+} // namespace Float
-/* namespace SimClock */ }
+} // namespace SimClock
void
setClockFrequency(Tick ticksPerSecond)
diff --git a/src/sim/core.hh b/src/sim/core.hh
index 8be1dd259..074ce32b6 100644
--- a/src/sim/core.hh
+++ b/src/sim/core.hh
@@ -55,7 +55,7 @@ extern double Hz;
extern double kHz;
extern double MHz;
extern double GHZ;
-/* namespace Float */ }
+} // namespace Float
namespace Int {
extern Tick s;
@@ -63,8 +63,8 @@ extern Tick ms;
extern Tick us;
extern Tick ns;
extern Tick ps;
-/* namespace Int */ }
-/* namespace SimClock */ }
+} // namespace Int
+} // namespace SimClock
void setClockFrequency(Tick ticksPerSecond);
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index 1ff67d2cb..2afea07ea 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -170,6 +170,6 @@ class InstTracer : public SimObject
-}; // namespace Trace
+} // namespace Trace
#endif // __INSTRECORD_HH__
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index 7a91bfbd4..683397116 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -326,4 +326,4 @@ switchcpu(ThreadContext *tc)
exitSimLoop("switchcpu");
}
-/* namespace PseudoInst */ }
+} // namespace PseudoInst
diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh
index 847dcede0..2f9671155 100644
--- a/src/sim/pseudo_inst.hh
+++ b/src/sim/pseudo_inst.hh
@@ -64,4 +64,4 @@ void m5checkpoint(ThreadContext *tc, Tick delay, Tick period);
void debugbreak(ThreadContext *tc);
void switchcpu(ThreadContext *tc);
-/* namespace PseudoInst */ }
+} // namespace PseudoInst
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index 07e1b2380..83861c185 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -201,4 +201,4 @@ StatEvent(bool dump, bool reset, Tick when, Tick repeat)
mainEventQueue.schedule(event, when);
}
-/* namespace Stats */ }
+} // namespace Stats
diff --git a/src/sim/stat_control.hh b/src/sim/stat_control.hh
index 1efa2554e..78031b666 100644
--- a/src/sim/stat_control.hh
+++ b/src/sim/stat_control.hh
@@ -36,6 +36,6 @@ namespace Stats {
void initSimStats();
void StatEvent(bool dump, bool reset, Tick when = curTick, Tick repeat = 0);
-/* namespace Stats */ }
+} // namespace Stats
#endif // __SIM_STAT_CONTROL_HH__