diff options
Diffstat (limited to 'src/sim')
-rw-r--r-- | src/sim/System.py | 5 | ||||
-rw-r--r-- | src/sim/system.cc | 4 | ||||
-rw-r--r-- | src/sim/system.hh | 61 |
3 files changed, 57 insertions, 13 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 69ae61e8f..031331375 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -35,7 +35,8 @@ from m5.proxy import * from SimpleMemory import * -class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] +class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing', + 'atomic_noncaching'] class System(MemObject): type = 'System' @@ -55,7 +56,7 @@ class System(MemObject): @classmethod def export_methods(cls, code): code(''' - Enums::MemoryMode getMemoryMode(); + Enums::MemoryMode getMemoryMode() const; void setMemoryMode(Enums::MemoryMode mode); ''') diff --git a/src/sim/system.cc b/src/sim/system.cc index 259ed3e88..03f8f8180 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -454,8 +454,8 @@ System::getMasterName(MasterID master_id) return masterIds[master_id]; } -const char *System::MemoryModeStrings[3] = {"invalid", "atomic", - "timing"}; +const char *System::MemoryModeStrings[4] = {"invalid", "atomic", "timing", + "atomic_noncaching"}; System * SystemParams::create() diff --git a/src/sim/system.hh b/src/sim/system.hh index d1b79bbf4..05b1f2077 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -120,20 +120,63 @@ class System : public MemObject BaseMasterPort& getMasterPort(const std::string &if_name, PortID idx = InvalidPortID); - static const char *MemoryModeStrings[3]; + static const char *MemoryModeStrings[4]; - Enums::MemoryMode - getMemoryMode() - { - assert(memoryMode); - return memoryMode; + /** @{ */ + /** + * Is the system in atomic mode? + * + * There are currently two different atomic memory modes: + * 'atomic', which supports caches; and 'atomic_noncaching', which + * bypasses caches. The latter is used by hardware virtualized + * CPUs. SimObjects are expected to use Port::sendAtomic() and + * Port::recvAtomic() when accessing memory in this mode. + */ + bool isAtomicMode() const { + return memoryMode == Enums::atomic || + memoryMode == Enums::atomic_noncaching; } - /** Change the memory mode of the system. This should only be called by the - * python!! - * @param mode Mode to change to (atomic/timing) + /** + * Is the system in timing mode? + * + * SimObjects are expected to use Port::sendTiming() and + * Port::recvTiming() when accessing memory in this mode. + */ + bool isTimingMode() const { + return memoryMode == Enums::timing; + } + + /** + * Should caches be bypassed? + * + * Some CPUs need to bypass caches to allow direct memory + * accesses, which is required for hardware virtualization. + */ + bool bypassCaches() const { + return memoryMode == Enums::atomic_noncaching; + } + /** @} */ + + /** @{ */ + /** + * Get the memory mode of the system. + * + * \warn This should only be used by the Python world. The C++ + * world should use one of the query functions above + * (isAtomicMode(), isTimingMode(), bypassCaches()). + */ + Enums::MemoryMode getMemoryMode() const { return memoryMode; } + + /** + * Change the memory mode of the system. + * + * \warn This should only be called by the Python! + * + * @param mode Mode to change to (atomic/timing/...) */ void setMemoryMode(Enums::MemoryMode mode); + /** @} */ PCEventQueue pcEventQueue; |