diff options
Diffstat (limited to 'src/sim')
| -rw-r--r-- | src/sim/System.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index 73124ecb9..88485fcf8 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -39,7 +39,7 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing'] class System(MemObject): type = 'System' - system_port = Port("System port") + system_port = MasterPort("System port") @classmethod def export_method_cxx_predecls(cls, code): |