diff options
Diffstat (limited to 'src/sim')
| -rw-r--r-- | src/sim/System.py | 2 | ||||
| -rw-r--r-- | src/sim/cxx_manager.cc | 21 | ||||
| -rw-r--r-- | src/sim/system.cc | 4 | ||||
| -rw-r--r-- | src/sim/system.hh | 6 |
4 files changed, 9 insertions, 24 deletions
diff --git a/src/sim/System.py b/src/sim/System.py index c012cb256..9928887b9 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -51,7 +51,7 @@ from m5.objects.SimpleMemory import * class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing', 'atomic_noncaching'] -class System(MemObject): +class System(SimObject): type = 'System' cxx_header = "sim/system.hh" system_port = MasterPort("System port") diff --git a/src/sim/cxx_manager.cc b/src/sim/cxx_manager.cc index 35d008d58..2ea3eaf0c 100644 --- a/src/sim/cxx_manager.cc +++ b/src/sim/cxx_manager.cc @@ -45,8 +45,8 @@ #include "base/str.hh" #include "base/trace.hh" #include "debug/CxxConfig.hh" -#include "mem/mem_object.hh" #include "sim/serialize.hh" +#include "sim/sim_object.hh" CxxConfigManager::CxxConfigManager(CxxConfigFileBase &configFile_) : configFile(configFile_), flags(configFile_.getFlags()), @@ -451,29 +451,14 @@ CxxConfigManager::bindPort( SimObject *slave_object, const std::string &slave_port_name, PortID slave_port_index) { - MemObject *master_mem_object = dynamic_cast<MemObject *>(master_object); - MemObject *slave_mem_object = dynamic_cast<MemObject *>(slave_object); - - if (!master_mem_object) { - throw Exception(master_object->name(), csprintf( - "Object isn't a mem object and so can have master port:" - " %s[%d]", master_port_name, master_port_index)); - } - - if (!slave_mem_object) { - throw Exception(slave_object->name(), csprintf( - "Object isn't a mem object and so can have slave port:" - " %s[%d]", slave_port_name, slave_port_index)); - } - /* FIXME, check slave_port_index against connection_count * defined for port, need getPortConnectionCount and a * getCxxConfigDirectoryEntry for each object. */ /* It would be nice to be able to catch the errors from these calls. */ - Port &master_port = master_mem_object->getPort( + Port &master_port = master_object->getPort( master_port_name, master_port_index); - Port &slave_port = slave_mem_object->getPort( + Port &slave_port = slave_object->getPort( slave_port_name, slave_port_index); if (master_port.isConnected()) { diff --git a/src/sim/system.cc b/src/sim/system.cc index 65ad6cdb0..74769654b 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -89,7 +89,7 @@ vector<System *> System::systemList; int System::numSystemsRunning = 0; System::System(Params *p) - : MemObject(p), _systemPort("system_port", this), + : SimObject(p), _systemPort("system_port", this), multiThread(p->multi_thread), pagePtr(0), init_param(p->init_param), @@ -444,7 +444,7 @@ System::unserialize(CheckpointIn &cp) void System::regStats() { - MemObject::regStats(); + SimObject::regStats(); for (uint32_t j = 0; j < numWorkIds ; j++) { workItemStats[j] = new Stats::Histogram(); diff --git a/src/sim/system.hh b/src/sim/system.hh index 6227ae660..d7a3b2008 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -58,7 +58,6 @@ #include "config/the_isa.hh" #include "enums/MemoryMode.hh" #include "mem/mem_master.hh" -#include "mem/mem_object.hh" #include "mem/physical.hh" #include "mem/port.hh" #include "mem/port_proxy.hh" @@ -66,6 +65,7 @@ #include "sim/futex_map.hh" #include "sim/redirect_path.hh" #include "sim/se_signal.hh" +#include "sim/sim_object.hh" /** * To avoid linking errors with LTO, only include the header if we @@ -81,7 +81,7 @@ class KvmVM; class ObjectFile; class ThreadContext; -class System : public MemObject +class System : public SimObject { private: @@ -97,7 +97,7 @@ class System : public MemObject /** * Create a system port with a name and an owner. */ - SystemPort(const std::string &_name, MemObject *_owner) + SystemPort(const std::string &_name, SimObject *_owner) : MasterPort(_name, _owner) { } bool recvTimingResp(PacketPtr pkt) override |