diff options
Diffstat (limited to 'src/systemc/core')
| -rw-r--r-- | src/systemc/core/SystemC.py | 6 | ||||
| -rw-r--r-- | src/systemc/core/sc_module.cc | 7 |
2 files changed, 12 insertions, 1 deletions
diff --git a/src/systemc/core/SystemC.py b/src/systemc/core/SystemC.py index 649d6d367..74b7cec14 100644 --- a/src/systemc/core/SystemC.py +++ b/src/systemc/core/SystemC.py @@ -25,7 +25,7 @@ # # Authors: Gabe Black -from m5.SimObject import SimObject +from m5.SimObject import SimObject, cxxMethod # This class represents the systemc kernel. There should be exactly one in the # simulation. It receives gem5 SimObject lifecycle callbacks (init, regStats, @@ -62,6 +62,10 @@ class SystemC_ScModule(SystemC_ScObject): cxx_class = 'sc_core::sc_module' cxx_header = 'systemc/ext/core/sc_module.hh' + @cxxMethod(return_value_policy="reference", cxx_name="gem5_getPort") + def getPort(self, if_name, iex): + return None + try: import _m5 except: diff --git a/src/systemc/core/sc_module.cc b/src/systemc/core/sc_module.cc index fc98aa3a0..ba9c76a0e 100644 --- a/src/systemc/core/sc_module.cc +++ b/src/systemc/core/sc_module.cc @@ -31,6 +31,7 @@ #include <string> #include <vector> +#include "base/logging.hh" #include "systemc/core/event.hh" #include "systemc/core/kernel.hh" #include "systemc/core/module.hh" @@ -114,6 +115,12 @@ sc_bind_proxy::sc_bind_proxy(sc_port_base &_port) : const sc_bind_proxy SC_BIND_PROXY_NIL; +::Port & +sc_module::gem5_getPort(const std::string &if_name, int idx) +{ + fatal("%s does not have any port named %s\n", name(), if_name); +} + sc_module::~sc_module() { delete _gem5_module; } void |