diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth')
10 files changed, 743 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp new file mode 100644 index 000000000..df19755c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp @@ -0,0 +1,99 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "bitwidth.h" + +void bitwidth::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<4> tmp2; + sc_bigint<6> tmp3; + sc_biguint<6> tmp4; + sc_bigint<8> tmp5; + sc_biguint<8> tmp6; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + //execute simple operations + // expected bitwidth 4 4 4 signed + tmp1 = tmp1 + tmp2; + // expected bitwidth 4 6 6 signed + tmp3 = tmp1 + tmp3; + // expected bitwidth 4 4 6 signed + tmp6 = tmp2 + tmp1; + // expected bitwidth 8 8 6 signed + tmp4 = tmp5 + tmp6; + // expected bitwidth 6 8 4 unsigned + tmp2 = tmp4 + tmp6; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f new file mode 100644 index 000000000..53a59162e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f @@ -0,0 +1,4 @@ +bitwidth/stimulus.cpp +bitwidth/display.cpp +bitwidth/bitwidth.cpp +bitwidth/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h new file mode 100644 index 000000000..9ced486ea --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h @@ -0,0 +1,120 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( bitwidth ) +{ + SC_HAS_PROCESS( bitwidth ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector6& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal_bool_vector8& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector6& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal_bool_vector8& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + bitwidth ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector6& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal_bool_vector8& IN_VALUE6, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector6& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal_bool_vector8& OUT_VALUE6, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h new file mode 100644 index 000000000..2a49981d9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp new file mode 100644 index 000000000..76acd9e62 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << in_data6.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h new file mode 100644 index 000000000..d35bb1abc --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector6& in_data3; // Input port + const sc_signal_bool_vector6& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal_bool_vector8& in_data6; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector4& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector6& IN_DATA3, + const sc_signal_bool_vector6& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal_bool_vector8& IN_DATA6, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_data6(IN_DATA6), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log new file mode 100644 index 000000000..d8f3d5726 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log @@ -0,0 +1,51 @@ +SystemC Simulation +Stimuli : 0 0 0 0 0 0 at 23 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 27 ns +Stimuli : 2 2 8 8 32 32 at 44 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 48 ns +Stimuli : 4 4 16 16 64 64 at 65 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 69 ns +Stimuli : 6 6 24 24 96 96 at 86 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 90 ns +Stimuli : -8 8 -32 32 -128 128 at 107 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 111 ns +Stimuli : -6 10 -24 40 -96 160 at 128 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 132 ns +Stimuli : -4 12 -16 48 -64 192 at 149 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 153 ns +Stimuli : -2 14 -8 56 -32 224 at 170 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 174 ns +Stimuli : 0 0 0 0 0 0 at 191 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 195 ns +Stimuli : 2 2 8 8 32 32 at 212 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 216 ns +Stimuli : 4 4 16 16 64 64 at 233 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 237 ns +Stimuli : 6 6 24 24 96 96 at 254 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 258 ns +Stimuli : -8 8 -32 32 -128 128 at 275 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 279 ns +Stimuli : -6 10 -24 40 -96 160 at 296 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 300 ns +Stimuli : -4 12 -16 48 -64 192 at 317 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 321 ns +Stimuli : -2 14 -8 56 -32 224 at 338 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 342 ns +Stimuli : 0 0 0 0 0 0 at 359 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 363 ns +Stimuli : 2 2 8 8 32 32 at 380 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 384 ns +Stimuli : 4 4 16 16 64 64 at 401 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 405 ns +Stimuli : 6 6 24 24 96 96 at 422 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 426 ns +Stimuli : -8 8 -32 32 -128 128 at 443 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 447 ns +Stimuli : -6 10 -24 40 -96 160 at 464 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 468 ns +Stimuli : -4 12 -16 48 -64 192 at 485 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 489 ns +Stimuli : -2 14 -8 56 -32 224 at 506 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 510 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp new file mode 100644 index 000000000..238dd032a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "bitwidth.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector6 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal_bool_vector8 stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector6 result_line4; + sc_signal_bool_vector8 result_line5; + sc_signal_bool_vector8 result_line6; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid); + + bitwidth bitwidth1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp new file mode 100644 index 000000000..15546d1b2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() { + sc_signed send_value1(4); + sc_unsigned send_value2(4); + sc_signed send_value3(6); + sc_unsigned send_value4(6); + sc_signed send_value5(8); + sc_unsigned send_value6(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value1 = 0; + send_value2 = 0; + send_value3 = 0; + send_value4 = 0; + send_value5 = 0; + send_value6 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + out_stimulus6.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_stimulus6.write( send_value6 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " + << send_value6 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+2; + send_value2 = send_value2+2; + send_value3 = send_value3+8; + send_value4 = send_value4+8; + send_value5 = send_value5+32; + send_value6 = send_value6+32; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h new file mode 100644 index 000000000..edbd6be48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector6& out_stimulus3; + sc_signal_bool_vector6& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal_bool_vector8& out_stimulus6; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector6& OUT_STIMULUS3, + sc_signal_bool_vector6& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal_bool_vector8& OUT_STIMULUS6, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_stimulus6(OUT_STIMULUS6), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF |