diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes')
11 files changed, 985 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp new file mode 100644 index 000000000..ec1d89946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp @@ -0,0 +1,143 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type not operations + + // signed(8) <- ~ unsigned(8) + tmp1r = ~ tmp2; + // unsigned(8) <- ~ long + tmp2r = ~ tmp3; + // long <- ~ char + tmp3r = ~ tmp6; + // int <- ~ short + tmp4r = ~ tmp5; + // short <- ~ int + tmp5r = ~ tmp4; + // char <- ~ char_array[0] + // tmp6r = ~ tmp8[0]; + tmp6r = ~ tmp8[0].to_bool(); + // bool <- ! bool; + tmp7r = !tmp7; + // sc_bool_vector(4) <- ~ sc_logic_vector(4) + tmp8r = ~ tmp9; + // sc_logic_vector(4) <- ~ sc_bool_vector(4) + tmp9r = ~ tmp9; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp new file mode 100644 index 000000000..75d3350de --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << (int)in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log new file mode 100644 index 000000000..4b372afbf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 -2 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 -1 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 -2 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 10100010 -37 -20019 -7626 -1 1 1010 1010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 11111001 10011101 -37 -20025 -7629 -2 0 1001 1001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 11111000 10011000 -37 -20031 -7632 -1 1 1000 1000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 11110111 10010011 -37 -20037 -7635 -2 0 0111 0111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 11110110 10001110 -37 -20043 -7638 -1 1 0110 0110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 11110101 10001001 -37 -20049 -7641 -2 0 0101 0101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 11110100 10000100 -37 -20055 -7644 -1 1 0100 0100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 11110011 01111111 -37 -20061 -7647 -2 0 0011 0011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 11110010 01111010 -37 -20067 -7650 -1 1 0010 0010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 11110001 01110101 -37 -20073 -7653 -2 0 0001 0001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 11110000 01110000 -37 -20079 -7656 -1 1 0000 0000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 11101111 01101011 -37 -20085 -7659 -2 0 1111 1111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 11101110 01100110 -37 -20091 -7662 -1 1 1110 1110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 11101101 01100001 -37 -20097 -7665 -2 0 1101 1101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 11101100 01011100 -37 -20103 -7668 -1 1 1100 1100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 11101011 01010111 -37 -20109 -7671 -2 0 1011 1011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 11101010 01010010 -37 -20115 -7674 -1 1 1010 1010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 11101001 01001101 -37 -20121 -7677 -2 0 1001 1001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 11101000 01001000 -37 -20127 -7680 -1 1 1000 1000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 11100111 01000011 -37 -20133 -7683 -2 0 0111 0111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 11100110 00111110 -37 -20139 -7686 -1 1 0110 0110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 11100101 00111001 -37 -20145 -7689 -2 0 0101 0101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 11100100 00110100 -37 -20151 -7692 -1 1 0100 0100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 11100011 00101111 -37 -20157 -7695 -2 0 0011 0011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 11100010 00101010 -37 -20163 -7698 -1 1 0010 0010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 11100001 00100101 -37 -20169 -7701 -2 0 0001 0001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 11100000 00100000 -37 -20175 -7704 -1 1 0000 0000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 11011111 00011011 -37 -20181 -7707 -2 0 1111 1111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 11011110 00010110 -37 -20187 -7710 -1 1 1110 1110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 11011101 00010001 -37 -20193 -7713 -2 0 1101 1101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 11011100 00001100 -37 -20199 -7716 -1 1 1100 1100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 11011011 00000111 -37 -20205 -7719 -2 0 1011 1011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 11011010 00000010 -37 -20211 -7722 -1 1 1010 1010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 11011001 11111101 -37 -20217 -7725 -2 0 1001 1001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 11011000 11111000 -37 -20223 -7728 -1 1 1000 1000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 11010111 11110011 -37 -20229 -7731 -2 0 0111 0111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 -1 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 new file mode 100644 index 000000000..d0ebd06c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 254 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 255 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 254 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 10100010 -37 -20019 -7626 255 1 1010 1010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 11111001 10011101 -37 -20025 -7629 254 0 1001 1001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 11111000 10011000 -37 -20031 -7632 255 1 1000 1000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 11110111 10010011 -37 -20037 -7635 254 0 0111 0111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 11110110 10001110 -37 -20043 -7638 255 1 0110 0110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 11110101 10001001 -37 -20049 -7641 254 0 0101 0101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 11110100 10000100 -37 -20055 -7644 255 1 0100 0100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 11110011 01111111 -37 -20061 -7647 254 0 0011 0011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 11110010 01111010 -37 -20067 -7650 255 1 0010 0010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 11110001 01110101 -37 -20073 -7653 254 0 0001 0001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 11110000 01110000 -37 -20079 -7656 255 1 0000 0000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 11101111 01101011 -37 -20085 -7659 254 0 1111 1111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 11101110 01100110 -37 -20091 -7662 255 1 1110 1110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 11101101 01100001 -37 -20097 -7665 254 0 1101 1101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 11101100 01011100 -37 -20103 -7668 255 1 1100 1100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 11101011 01010111 -37 -20109 -7671 254 0 1011 1011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 11101010 01010010 -37 -20115 -7674 255 1 1010 1010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 11101001 01001101 -37 -20121 -7677 254 0 1001 1001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 11101000 01001000 -37 -20127 -7680 255 1 1000 1000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 11100111 01000011 -37 -20133 -7683 254 0 0111 0111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 11100110 00111110 -37 -20139 -7686 255 1 0110 0110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 11100101 00111001 -37 -20145 -7689 254 0 0101 0101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 11100100 00110100 -37 -20151 -7692 255 1 0100 0100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 11100011 00101111 -37 -20157 -7695 254 0 0011 0011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 11100010 00101010 -37 -20163 -7698 255 1 0010 0010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 11100001 00100101 -37 -20169 -7701 254 0 0001 0001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 11100000 00100000 -37 -20175 -7704 255 1 0000 0000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 11011111 00011011 -37 -20181 -7707 254 0 1111 1111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 11011110 00010110 -37 -20187 -7710 255 1 1110 1110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 11011101 00010001 -37 -20193 -7713 254 0 1101 1101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 11011100 00001100 -37 -20199 -7716 255 1 1100 1100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 11011011 00000111 -37 -20205 -7719 254 0 1011 1011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 11011010 00000010 -37 -20211 -7722 255 1 1010 1010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 11011001 11111101 -37 -20217 -7725 254 0 1001 1001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 11011000 11111000 -37 -20223 -7728 255 1 1000 1000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 11010111 11110011 -37 -20229 -7731 254 0 0111 0111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 255 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + |