diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1')
10 files changed, 717 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log new file mode 100644 index 000000000..d5f651425 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 31 31 00001111 00011111 00011111 at 17 ns +Display : 31 31 00001111 00011111 00011111 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 31 31 00001111 00011111 00011111 at 28 ns +Display : 31 31 00001111 00011111 00011111 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 31 31 00011111 00011111 00011111 at 39 ns +Display : 31 31 00011111 00011111 00011111 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 63 00101111 00111111 00111111 at 50 ns +Display : 63 63 00101111 00111111 00111111 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 63 63 00101111 00111111 00111111 at 61 ns +Display : 63 63 00101111 00111111 00111111 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 63 63 00111111 00111111 00111111 at 72 ns +Display : 63 63 00111111 00111111 00111111 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 95 95 01001111 01011111 01011111 at 83 ns +Display : 95 95 01001111 01011111 01011111 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 95 95 01001111 01011111 01011111 at 94 ns +Display : 95 95 01001111 01011111 01011111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 95 95 01011111 01011111 01011111 at 105 ns +Display : 95 95 01011111 01011111 01011111 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 127 127 01101111 01111111 01111111 at 116 ns +Display : 127 127 01101111 01111111 01111111 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 127 127 01101111 01111111 01111111 at 127 ns +Display : 127 127 01101111 01111111 01111111 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 127 127 01111111 01111111 01111111 at 138 ns +Display : 127 127 01111111 01111111 01111111 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp new file mode 100644 index 000000000..fb587275d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "or_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + or_1 or1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp new file mode 100644 index 000000000..e65fdbaf1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "or_1.h" + +void or_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 | 0x0f | 0x12; + tmp2 = tmp2 | 0x0f | 0x13 ; + tmp3 = tmp3 | tmp3_tmp; + tmp4 = tmp4 | 0x0f | 0x14 ; + tmp5 = tmp5 | 0x0f | 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 |= 0x03; + tmp2 |= 0x03; + tmp3 |= tmp3_tmp; + tmp4 |= 0x03; + tmp5 |= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f new file mode 100644 index 000000000..8b7bff4d2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f @@ -0,0 +1,4 @@ +or_1/display.cpp +or_1/main.cpp +or_1/or_1.cpp +or_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h new file mode 100644 index 000000000..99285a543 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( or_1 ) +{ + SC_HAS_PROCESS( or_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + or_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF |