diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/bitwise/or')
20 files changed, 1652 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp new file mode 100644 index 000000000..eeacba45c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp @@ -0,0 +1,123 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + int tmp7[2]; + char tmp8[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmp7[0] = 12; + tmp7[1] = 0; + tmp8[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmp8[0] = in_value7.read(); + + out_ack.write(true); + + //execute mixed data type or operations + + // signed(8) <- signed(8) & unsigned(8) + tmp1r = tmp1 | tmp2; + // unsigned(8) <- char & long + tmp2r = tmp6 | tmp3; + // long <- int & char + tmp3r = tmp4 | tmp6; + // int <- int & short + tmp4r = tmp4 | tmp5; + // short <- short & const + tmp5r = tmp5 | 5; + // char <- char_array[0] & int_array[1] + tmp6r = tmp8[0] | tmp7[1]; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f new file mode 100644 index 000000000..c767ce1c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/datatypes.cpp +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h new file mode 100644 index 000000000..3332046ad --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h @@ -0,0 +1,127 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp new file mode 100644 index 000000000..258461c24 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h new file mode 100644 index 000000000..3c2ece81a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h @@ -0,0 +1,88 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log new file mode 100644 index 000000000..d6f00f117 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A +Display: 01010111 01101110 -123420 -106528 20005 A +Stimuli: 87 3 12345683 -123453 20006 $ B +Display: 01010111 01110111 -123417 -106521 20007 B +Stimuli: 89 4 12345688 -123450 20012 $ C +Display: 01011101 01111100 -123418 -106514 20013 C +Stimuli: 91 5 12345693 -123447 20018 $ D +Display: 01011111 01111101 -123411 -106501 20023 D +Stimuli: 93 6 12345698 -123444 20024 $ E +Display: 01011111 01100110 -123412 -106500 20029 E +Stimuli: 95 7 12345703 -123441 20030 $ F +Display: 01011111 01100111 -123409 -106497 20031 F +Stimuli: 97 8 12345708 -123438 20036 $ G +Display: 01101001 01101100 -123402 -106538 20037 G +Stimuli: 99 9 12345713 -123435 20042 $ H +Display: 01101011 01110101 -123403 -106529 20047 H +Stimuli: 101 10 12345718 -123432 20048 $ I +Display: 01101111 01110110 -123396 -106536 20053 I +Stimuli: 103 11 12345723 -123429 20054 $ J +Display: 01101111 01111111 -123393 -106529 20055 J +Stimuli: 105 12 12345728 -123426 20060 $ K +Display: 01101101 10100100 -123394 -106530 20061 K +Stimuli: 107 13 12345733 -123423 20066 $ L +Display: 01101111 10100101 -123419 -106525 20071 L +Stimuli: 109 14 12345738 -123420 20072 $ M +Display: 01101111 10101110 -123420 -106516 20077 M +Stimuli: 111 15 12345743 -123417 20078 $ N +Display: 01101111 10101111 -123417 -106513 20079 N +Stimuli: 113 16 12345748 -123414 20084 $ O +Display: 01110001 10110100 -123410 -106498 20085 O +Stimuli: 115 17 12345753 -123411 20090 $ P +Display: 01110011 10111101 -123411 -106497 20095 P +Stimuli: 117 18 12345758 -123408 20096 $ Q +Display: 01110111 10111110 -123404 -106512 20101 Q +Stimuli: 119 19 12345763 -123405 20102 $ R +Display: 01110111 10100111 -123401 -106505 20103 R +Stimuli: 121 20 12345768 -123402 20108 $ S +Display: 01111101 10101100 -123402 -106498 20109 S +Stimuli: 123 21 12345773 -123399 20114 $ T +Display: 01111111 10101101 -123395 -106501 20119 T +Stimuli: 125 22 12345778 -123396 20120 $ U +Display: 01111111 10110110 -123396 -106500 20125 U +Stimuli: 127 23 12345783 -123393 20126 $ V +Display: 01111111 10110111 -123393 -106497 20127 V +Stimuli: -127 24 12345788 -123390 20132 $ W +Display: 10011001 10111100 -123354 -106842 20133 W +Stimuli: -125 25 12345793 -123387 20138 $ X +Display: 10011011 11100101 -123355 -106833 20143 X +Stimuli: -123 26 12345798 -123384 20144 $ Y +Display: 10011111 11100110 -123348 -106824 20149 Y +Stimuli: -121 27 12345803 -123381 20150 $ Z +Display: 10011111 11101111 -123345 -106817 20151 Z +Stimuli: -119 28 12345808 -123378 20156 $ [ +Display: 10011101 11110100 -123346 -106818 20157 [ +Stimuli: -117 29 12345813 -123375 20162 $ \ +Display: 10011111 11110101 -123339 -106797 20167 \ +Stimuli: -115 30 12345818 -123372 20168 $ ] +Display: 10011111 11111110 -123340 -106788 20173 ] +Stimuli: -113 31 12345823 -123369 20174 $ ^ +Display: 10011111 11111111 -123337 -106785 20175 ^ +Stimuli: -111 32 12345828 -123366 20180 $ _ +Display: 10110001 11100100 -123330 -106786 20181 _ +Stimuli: -109 33 12345833 -123363 20186 $ ` +Display: 10110011 11101101 -123331 -106785 20191 ` +Stimuli: -107 34 12345838 -123360 20192 $ a +Display: 10110111 11101110 -123356 -106784 20197 a +Stimuli: -105 35 12345843 -123357 20198 $ b +Display: 10110111 11110111 -123353 -106777 20199 b +Stimuli: -103 36 12345848 -123354 20204 $ c +Display: 10111101 11111100 -123354 -106770 20205 c +Stimuli: -101 37 12345853 -123351 20210 $ d +Display: 10111111 11111101 -123347 -106757 20215 d +Stimuli: -99 38 12345858 -123348 20216 $ e +Display: 10111111 00100110 -123348 -106756 20221 e +Stimuli: -97 39 12345863 -123345 20222 $ f +Display: 10111111 00100111 -123345 -106753 20223 f +Stimuli: -95 40 12345868 -123342 20228 $ g +Display: 10101001 00101100 -123338 -106698 20229 g +Stimuli: -93 41 12345873 -123339 20234 $ h +Display: 10101011 00110101 -123339 -106689 20239 h +Stimuli: -91 42 12345878 -123336 20240 $ i +Display: 10101111 00110110 -123332 -106696 20245 i +Stimuli: -89 43 12345883 -123333 20246 $ j +Display: 10101111 00111111 -123329 -106689 20247 j +Stimuli: -87 44 12345888 -123330 20252 $ k +Display: 10101101 00100100 -123330 -106690 20253 k +Stimuli: -85 45 12345893 -123327 20258 $ l +Display: 10101111 00100101 -123291 -106653 20263 l +Stimuli: -83 46 12345898 -123324 20264 $ m +Display: 10101111 00101110 -123292 -106644 20269 m +Stimuli: -81 47 12345903 -123321 20270 $ n +Display: 10101111 00101111 -123289 -106641 20271 n +Stimuli: -79 48 12345908 -123318 20276 $ o +Display: 10110001 00110100 -123282 -106626 20277 o +Stimuli: -77 49 12345913 -123315 20282 $ p +Display: 10110011 00111101 -123283 -106625 20287 p +Stimuli: -75 50 12345918 -123312 20288 $ q +Display: 10110111 00111110 -123276 -106672 20293 q +Stimuli: -73 51 12345923 -123309 20294 $ r +Display: 10110111 01100111 -123273 -106665 20295 r +Stimuli: -71 52 12345928 -123306 20300 $ s +Display: 10111101 01101100 -123274 -106658 20301 s +Stimuli: -69 53 12345933 -123303 20306 $ t +Display: 10111111 01101101 -123267 -106661 20311 t +Stimuli: -67 54 12345938 -123300 20312 $ u +Display: 10111111 01110110 -123268 -106660 20317 u +Stimuli: -65 55 12345943 -123297 20318 $ v +Display: 10111111 01110111 -123265 -106657 20319 v +Stimuli: -63 56 12345948 -123294 20324 $ w +Display: 11111001 01111100 -123290 -106650 20325 w +Stimuli: -61 57 12345953 -123291 20330 $ x +Display: 11111011 01100101 -123291 -106641 20335 x +Stimuli: -59 58 12345958 -123288 20336 $ y +Display: 11111111 01100110 -123284 -106632 20341 y +Stimuli: -57 59 12345963 -123285 20342 $ z +Display: 11111111 01101111 -123281 -106625 20343 z +Stimuli: -55 60 12345968 -123282 20348 $ { +Display: 11111101 01110100 -123282 -106626 20349 { +Stimuli: -53 61 12345973 -123279 20354 $ | +Display: 11111111 01110101 -123275 -106509 20359 | +Stimuli: -51 62 12345978 -123276 20360 $ } +Display: 11111111 01111110 -123276 -106500 20365 } +Stimuli: -49 63 12345983 -123273 20366 $ ~ +Display: 11111111 01111111 -123273 -106497 20367 ~ +Stimuli: -47 64 12345988 -123270 20372 $ +Display: 11010001 10100100 -123266 -106498 20373 +Stimuli: -45 65 12345993 -123267 20378 $ € +Display: 11010011 10101101 -123267 -106497 20383 € +Stimuli: -43 66 12345998 -123264 20384 $ +Display: 11010111 10101110 -123228 -106592 20389 +Stimuli: -41 67 12346003 -123261 20390 $ ‚ +Display: 11010111 10110111 -123225 -106585 20391 ‚ +Stimuli: -39 68 12346008 -123258 20396 $ ƒ +Display: 11011101 10111100 -123226 -106578 20397 ƒ +Stimuli: -37 69 12346013 -123255 20402 $ „ +Display: 11011111 10111101 -123219 -106565 20407 „ +Stimuli: -35 70 12346018 -123252 20408 $ … +Display: 11011111 10100110 -123220 -106564 20413 … +Stimuli: -33 71 12346023 -123249 20414 $ † +Display: 11011111 10100111 -123217 -106561 20415 † +Stimuli: -31 72 12346028 -123246 20420 $ ‡ +Display: 11101001 10101100 -123210 -106538 20421 ‡ +Stimuli: -29 73 12346033 -123243 20426 $ ˆ +Display: 11101011 10110101 -123211 -106529 20431 ˆ +Stimuli: -27 74 12346038 -123240 20432 $ ‰ +Display: 11101111 10110110 -123204 -106536 20437 ‰ +Stimuli: -25 75 12346043 -123237 20438 $ Š +Display: 11101111 10111111 -123201 -106529 20439 Š +Stimuli: -23 76 12346048 -123234 20444 $ ‹ +Display: 11101101 11100100 -123202 -106530 20445 ‹ +Stimuli: -21 77 12346053 -123231 20450 $ Œ +Display: 11101111 11100101 -123227 -106525 20455 Œ +Stimuli: -19 78 12346058 -123228 20456 $ +Display: 11101111 11101110 -123228 -106516 20461 +Stimuli: -17 79 12346063 -123225 20462 $ Ž +Display: 11101111 11101111 -123225 -106513 20463 Ž +Stimuli: -15 80 12346068 -123222 20468 $ +Display: 11110001 11110100 -123218 -106498 20469 +Stimuli: -13 81 12346073 -123219 20474 $ +Display: 11110011 11111101 -123219 -106497 20479 +Stimuli: -11 82 12346078 -123216 20480 $ ‘ +Display: 11110111 11111110 -123212 -106832 20485 ‘ +Stimuli: -9 83 12346083 -123213 20486 $ ’ +Display: 11110111 11100111 -123209 -106825 20487 ’ +Stimuli: -7 84 12346088 -123210 20492 $ “ +Display: 11111101 11101100 -123210 -106818 20493 “ +Stimuli: -5 85 12346093 -123207 20498 $ ” +Display: 11111111 11101101 -123203 -106821 20503 ” +Stimuli: -3 86 12346098 -123204 20504 $ • +Display: 11111111 11110110 -123204 -106820 20509 • +Stimuli: -1 87 12346103 -123201 20510 $ – +Display: 11111111 11110111 -123201 -106817 20511 – +Stimuli: 1 88 12346108 -123198 20516 $ — +Display: 01011001 11111100 -123162 -106778 20517 — +Stimuli: 3 89 12346113 -123195 20522 $ ˜ +Display: 01011011 00100101 -123163 -106769 20527 ˜ +Stimuli: 5 90 12346118 -123192 20528 $ ™ +Display: 01011111 00100110 -123156 -106760 20533 ™ +Stimuli: 7 91 12346123 -123189 20534 $ š +Display: 01011111 00101111 -123153 -106753 20535 š +Stimuli: 9 92 12346128 -123186 20540 $ › +Display: 01011101 00110100 -123154 -106754 20541 › +Stimuli: 11 93 12346133 -123183 20546 $ œ +Display: 01011111 00110101 -123147 -106797 20551 œ +Stimuli: 13 94 12346138 -123180 20552 $ +Display: 01011111 00111110 -123148 -106788 20557 +Stimuli: 15 95 12346143 -123177 20558 $ ž +Display: 01011111 00111111 -123145 -106785 20559 ž +Stimuli: 17 96 12346148 -123174 20564 $ Ÿ +Display: 01110001 00100100 -123138 -106786 20565 Ÿ +Stimuli: 19 97 12346153 -123171 20570 $ +Display: 01110011 00101101 -123139 -106785 20575 +Stimuli: 21 98 12346158 -123168 20576 $ ¡ +Display: 01110111 00101110 -123164 -106784 20581 ¡ +Stimuli: 23 99 12346163 -123165 20582 $ ¢ +Display: 01110111 00110111 -123161 -106777 20583 ¢ +Stimuli: 25 100 12346168 -123162 20588 $ £ +Display: 01111101 00111100 -123162 -106770 20589 £ +Stimuli: 27 101 12346173 -123159 20594 $ ¤ +Display: 01111111 00111101 -123155 -106757 20599 ¤ +Stimuli: 29 102 12346178 -123156 20600 $ ¥ + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp new file mode 100644 index 000000000..319d97eb5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Stan Liao, Synopsys, Inc., 1999-10-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + input_valid = 0; + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp new file mode 100644 index 000000000..aff6ff983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h new file mode 100644 index 000000000..fbb96b57b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log new file mode 100644 index 000000000..d5f651425 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 31 31 00001111 00011111 00011111 at 17 ns +Display : 31 31 00001111 00011111 00011111 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 31 31 00001111 00011111 00011111 at 28 ns +Display : 31 31 00001111 00011111 00011111 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 31 31 00011111 00011111 00011111 at 39 ns +Display : 31 31 00011111 00011111 00011111 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 63 00101111 00111111 00111111 at 50 ns +Display : 63 63 00101111 00111111 00111111 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 63 63 00101111 00111111 00111111 at 61 ns +Display : 63 63 00101111 00111111 00111111 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 63 63 00111111 00111111 00111111 at 72 ns +Display : 63 63 00111111 00111111 00111111 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 95 95 01001111 01011111 01011111 at 83 ns +Display : 95 95 01001111 01011111 01011111 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 95 95 01001111 01011111 01011111 at 94 ns +Display : 95 95 01001111 01011111 01011111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 95 95 01011111 01011111 01011111 at 105 ns +Display : 95 95 01011111 01011111 01011111 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 127 127 01101111 01111111 01111111 at 116 ns +Display : 127 127 01101111 01111111 01111111 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 127 127 01101111 01111111 01111111 at 127 ns +Display : 127 127 01101111 01111111 01111111 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 127 127 01111111 01111111 01111111 at 138 ns +Display : 127 127 01111111 01111111 01111111 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp new file mode 100644 index 000000000..fb587275d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "or_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + or_1 or1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp new file mode 100644 index 000000000..e65fdbaf1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "or_1.h" + +void or_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 | 0x0f | 0x12; + tmp2 = tmp2 | 0x0f | 0x13 ; + tmp3 = tmp3 | tmp3_tmp; + tmp4 = tmp4 | 0x0f | 0x14 ; + tmp5 = tmp5 | 0x0f | 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 |= 0x03; + tmp2 |= 0x03; + tmp3 |= tmp3_tmp; + tmp4 |= 0x03; + tmp5 |= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f new file mode 100644 index 000000000..8b7bff4d2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f @@ -0,0 +1,4 @@ +or_1/display.cpp +or_1/main.cpp +or_1/or_1.cpp +or_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h new file mode 100644 index 000000000..99285a543 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( or_1 ) +{ + SC_HAS_PROCESS( or_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + or_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF |