diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes')
10 files changed, 900 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp new file mode 100644 index 000000000..5b863a7ed --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp @@ -0,0 +1,142 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type xor operations + + // signed(8) <- signed(8) ^ unsigned(8) + tmp1r = tmp1 ^ tmp2; + // unsigned(8) <- char ^ long + tmp2r = tmp6 ^ tmp3; + // long <- int ^ char + tmp3r = tmp4 ^ tmp6; + // int <- int ^ short + tmp4r = tmp4 ^ tmp5; + // short <- short ^ const + tmp5r = tmp5 ^ 5; + // char <- char_array[0] ^ int_array[1] + tmp6r = tmpb[0] ^ tmpa[1]; + // bool <- bool ^ bool; + tmp7r = tmp7 ^ tmp7; + // sc_bool_vector(4) <- sc_bool_vector(4) ^ sc_logic_vector(4) + tmp8r = tmp8 ^ tmp9; + // sc_logic_vector(4) <- sc_bool_vector(4) ^ "0111" + tmp9r = tmp9 ^ sc_bv<4>( "0111" ); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp new file mode 100644 index 000000000..0c6fdf20e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log new file mode 100644 index 000000000..05838b4cf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 01010111 01101010 -123420 -109600 20005 > 0 0011 0101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 01010100 01110111 -123417 -109595 20003 = 0 0001 0100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 01011101 01111100 -123422 -109590 20009 < 0 0111 0011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 01011110 01111001 -123411 -109573 20023 ; 0 0001 0010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 01011011 01000110 -123416 -109580 20029 : 0 0011 0001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 01011000 01000011 -123413 -109583 20027 9 0 0001 0000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 01101001 01001000 -123402 -109674 20033 8 0 1111 1111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 01101010 01010101 -123407 -109665 20047 7 0 0001 1110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 01101111 01010010 -123396 -109688 20053 6 0 0011 1101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 01101100 01011111 -123393 -109683 20051 5 0 0001 1100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 01100101 10100100 -123398 -109694 20057 4 0 0111 1011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 01100110 10100001 -123451 -109693 20071 3 0 0001 1010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 01100011 10101110 -123456 -109684 20077 2 0 0011 1001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 01100000 10101011 -123453 -109687 20075 1 0 0001 1000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 01100001 10110000 -123442 -109666 20081 0 0 1111 0111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 01100010 10111101 -123447 -109673 20095 / 0 0001 0110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 01100111 10111010 -123436 -109712 20101 . 0 0011 0101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 01100100 10000111 -123433 -109707 20099 - 0 0001 0100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 01101101 10001100 -123438 -109702 20105 , 0 0111 0011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 01101110 10001001 -123427 -109717 20119 + 0 0001 0010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 01101011 10010110 -123432 -109724 20125 * 0 0011 0001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 01101000 10010011 -123429 -109727 20123 ) 0 0001 0000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 10011001 10011000 -123354 -110426 20129 ( 0 1111 1111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 10011010 11100101 -123359 -110417 20143 ' 0 0001 1110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 10011111 11100010 -123348 -110408 20149 & 0 0011 1101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 10011100 11101111 -123345 -110403 20147 % 0 0001 1100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 10010101 11110100 -123350 -110414 20153 $ 0 0111 1011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 10010110 11110001 -123339 -110381 20167 # 0 0001 1010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 10010011 11111110 -123344 -110372 20173 " 0 0011 1001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 10010000 11111011 -123341 -110375 20171 ! 0 0001 1000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 10110001 11000000 -123330 -110386 20177 0 1111 0111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 10110010 11001101 -123335 -110393 20191 0 0001 0110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 10110111 11001010 -123388 -110400 20197 0 0011 0101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 10110100 11010111 -123385 -110395 20195 0 0001 0100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 10111101 11011100 -123390 -110390 20201 0 0111 0011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 10111110 11011001 -123379 -110373 20215 0 0001 0010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 10111011 00100110 -123384 -110380 20221 0 0011 0001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 10111000 00100011 -123381 -110383 20219 0 0001 0000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 10001001 00101000 -123370 -110282 20225 0 1111 1111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 10001010 00110101 -123375 -110273 20239 0 0001 1110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + |