diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/bitwise')
123 files changed, 10366 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp new file mode 100644 index 000000000..5a8b81974 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + and_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "and_1.h" + +void and_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 & 0x0f & 0x12; + tmp2 = tmp2 & 0x0f & 0x13 ; + tmp3 = tmp3 & tmp3_tmp; + tmp4 = tmp4 & 0x0f & 0x14 ; + tmp5 = tmp5 & 0x0f & 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 &= 0x03; + tmp2 &= 0x03; + tmp3 &= tmp3_tmp; + tmp4 &= 0x03; + tmp5 &= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f new file mode 100644 index 000000000..606aecf73 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f @@ -0,0 +1,4 @@ +and_1/stimulus.cpp +and_1/display.cpp +and_1/and_1.cpp +and_1/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h new file mode 100644 index 000000000..2e88eb916 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + and_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( and_1 ) +{ + SC_HAS_PROCESS( and_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + and_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log new file mode 100644 index 000000000..dfc053eb3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 0 1 00000001 00000000 00000001 at 17 ns +Display : 0 1 00000001 00000000 00000001 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 0 0 00001100 00000100 00000100 at 28 ns +Display : 0 0 00000000 00000000 00000000 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 2 3 00000111 00000100 00000101 at 39 ns +Display : 2 3 00000011 00000000 00000001 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 2 2 00000010 00000000 00000000 at 50 ns +Display : 2 2 00000010 00000000 00000000 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 0 1 00001101 00000100 00000101 at 61 ns +Display : 0 1 00000001 00000000 00000001 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 0 0 00001000 00000000 00000000 at 72 ns +Display : 0 0 00000000 00000000 00000000 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 2 3 00000011 00000000 00000001 at 83 ns +Display : 2 3 00000011 00000000 00000001 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 2 2 00001110 00000100 00000100 at 94 ns +Display : 2 2 00000010 00000000 00000000 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 0 1 00001001 00000000 00000001 at 105 ns +Display : 0 1 00000001 00000000 00000001 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 0 0 00000100 00000100 00000100 at 116 ns +Display : 0 0 00000000 00000000 00000000 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 2 3 00001111 00000100 00000101 at 127 ns +Display : 2 3 00000011 00000000 00000001 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 2 2 00001010 00000000 00000000 at 138 ns +Display : 2 2 00000010 00000000 00000000 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp new file mode 100644 index 000000000..79b1c4704 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "and_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + and_1 and1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp new file mode 100644 index 000000000..8664cf6ec --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_bigint<8> send_value4; + sc_biguint<8> send_value5; + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp new file mode 100644 index 000000000..0cbeaaf72 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp @@ -0,0 +1,142 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type and operations + + // signed(8) <- signed(8) & unsigned(8) + tmp1r = tmp1 & tmp2; + // unsigned(8) <- char & long + tmp2r = tmp6 & tmp3; + // long <- int & char + tmp3r = tmp4 & tmp6; + // int <- int & short + tmp4r = tmp4 & tmp5; + // short <- short & const + tmp5r = tmp5 & 5; + // char <- char_array[0] & int_array[1] + tmp6r = tmpb[0] & tmpa[1]; + // bool <- bool & bool; + tmp7r = tmp7 & tmp7; + // sc_bool_vector(4) <- sc_bool_vector(4) & sc_logic_vector(4) + tmp8r = tmp8 & tmp9; + // sc_logic_vector(4) <- sc_bool_vector(4) & "0111" + tmp9r = tmp9 & sc_bv<4>( "0111" ); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h new file mode 100644 index 000000000..547119370 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp new file mode 100644 index 000000000..0c6fdf20e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h new file mode 100644 index 000000000..3bc92072f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log new file mode 100644 index 000000000..0af19af8b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 00000000 00000100 0 3072 0 A 1 0000 0010 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 00000011 00000000 0 3074 4 B 0 0010 0011 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 00000000 00000000 4 3076 4 C 1 0000 0100 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 00000001 00000100 0 3072 0 D 0 0100 0101 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 00000100 00100000 4 3080 0 E 1 0100 0110 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 00000111 00100100 4 3086 4 F 0 0110 0111 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 00000000 00100100 0 3136 4 G 1 0000 0000 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 00000001 00100000 4 3136 0 H 0 1000 0001 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 00000000 00100100 0 3152 0 I 1 1000 0010 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 00000011 00100000 0 3154 4 J 0 1010 0011 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 00001000 00000000 4 3164 4 K 1 1000 0100 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 00001001 00000100 32 3168 0 L 0 1100 0101 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 00001100 00000000 36 3168 0 M 1 1100 0110 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 00001111 00000100 36 3174 4 N 0 1110 0111 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 00010000 00000100 32 3168 4 O 1 0000 0000 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 00010001 00000000 36 3176 0 P 0 0000 0001 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 00010000 00000100 32 3200 0 Q 1 0000 0010 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 00010011 00100000 32 3202 4 R 0 0010 0011 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 00010000 00100000 36 3204 4 S 1 0000 0100 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 00010001 00100100 32 3216 0 T 0 0100 0101 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 00010100 00100000 36 3224 0 U 1 0100 0110 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 00010111 00100100 36 3230 4 V 0 0110 0111 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 00000000 00100100 0 3584 4 W 1 0000 0000 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 00000001 00000000 4 3584 0 X 0 1000 0001 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 00000000 00000100 0 3584 0 Y 1 1000 0010 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 00000011 00000000 0 3586 4 Z 0 1010 0011 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 00001000 00000000 4 3596 4 [ 1 1000 0100 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 00001001 00000100 0 3584 0 \ 0 1100 0101 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 00001100 00000000 4 3584 0 ] 1 1100 0110 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 00001111 00000100 4 3590 4 ^ 0 1110 0111 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 00000000 00100100 0 3600 4 _ 1 0000 0000 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 00000001 00100000 4 3608 0 ` 0 0000 0001 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 00000000 00100100 32 3616 0 a 1 0000 0010 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 00000011 00100000 32 3618 4 b 0 0010 0011 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 00000000 00100000 36 3620 4 c 1 0000 0100 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 00000001 00100100 32 3616 0 d 0 0100 0101 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 00000100 00000000 36 3624 0 e 1 0100 0110 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 00000111 00000100 36 3630 4 f 0 0110 0111 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 00100000 00000100 32 3584 4 g 1 0000 0000 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 00100001 00000000 36 3584 0 h 0 1000 0001 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h new file mode 100644 index 000000000..5fa7f4b64 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp new file mode 100644 index 000000000..ec1d89946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp @@ -0,0 +1,143 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type not operations + + // signed(8) <- ~ unsigned(8) + tmp1r = ~ tmp2; + // unsigned(8) <- ~ long + tmp2r = ~ tmp3; + // long <- ~ char + tmp3r = ~ tmp6; + // int <- ~ short + tmp4r = ~ tmp5; + // short <- ~ int + tmp5r = ~ tmp4; + // char <- ~ char_array[0] + // tmp6r = ~ tmp8[0]; + tmp6r = ~ tmp8[0].to_bool(); + // bool <- ! bool; + tmp7r = !tmp7; + // sc_bool_vector(4) <- ~ sc_logic_vector(4) + tmp8r = ~ tmp9; + // sc_logic_vector(4) <- ~ sc_bool_vector(4) + tmp9r = ~ tmp9; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp new file mode 100644 index 000000000..75d3350de --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << (int)in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log new file mode 100644 index 000000000..4b372afbf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 -2 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 -1 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 -2 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 10100010 -37 -20019 -7626 -1 1 1010 1010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 11111001 10011101 -37 -20025 -7629 -2 0 1001 1001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 11111000 10011000 -37 -20031 -7632 -1 1 1000 1000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 11110111 10010011 -37 -20037 -7635 -2 0 0111 0111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 11110110 10001110 -37 -20043 -7638 -1 1 0110 0110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 11110101 10001001 -37 -20049 -7641 -2 0 0101 0101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 11110100 10000100 -37 -20055 -7644 -1 1 0100 0100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 11110011 01111111 -37 -20061 -7647 -2 0 0011 0011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 11110010 01111010 -37 -20067 -7650 -1 1 0010 0010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 11110001 01110101 -37 -20073 -7653 -2 0 0001 0001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 11110000 01110000 -37 -20079 -7656 -1 1 0000 0000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 11101111 01101011 -37 -20085 -7659 -2 0 1111 1111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 11101110 01100110 -37 -20091 -7662 -1 1 1110 1110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 11101101 01100001 -37 -20097 -7665 -2 0 1101 1101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 11101100 01011100 -37 -20103 -7668 -1 1 1100 1100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 11101011 01010111 -37 -20109 -7671 -2 0 1011 1011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 11101010 01010010 -37 -20115 -7674 -1 1 1010 1010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 11101001 01001101 -37 -20121 -7677 -2 0 1001 1001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 11101000 01001000 -37 -20127 -7680 -1 1 1000 1000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 11100111 01000011 -37 -20133 -7683 -2 0 0111 0111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 11100110 00111110 -37 -20139 -7686 -1 1 0110 0110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 11100101 00111001 -37 -20145 -7689 -2 0 0101 0101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 11100100 00110100 -37 -20151 -7692 -1 1 0100 0100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 11100011 00101111 -37 -20157 -7695 -2 0 0011 0011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 11100010 00101010 -37 -20163 -7698 -1 1 0010 0010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 11100001 00100101 -37 -20169 -7701 -2 0 0001 0001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 11100000 00100000 -37 -20175 -7704 -1 1 0000 0000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 11011111 00011011 -37 -20181 -7707 -2 0 1111 1111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 11011110 00010110 -37 -20187 -7710 -1 1 1110 1110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 11011101 00010001 -37 -20193 -7713 -2 0 1101 1101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 11011100 00001100 -37 -20199 -7716 -1 1 1100 1100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 11011011 00000111 -37 -20205 -7719 -2 0 1011 1011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 11011010 00000010 -37 -20211 -7722 -1 1 1010 1010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 11011001 11111101 -37 -20217 -7725 -2 0 1001 1001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 11011000 11111000 -37 -20223 -7728 -1 1 1000 1000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 11010111 11110011 -37 -20229 -7731 -2 0 0111 0111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 -1 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 new file mode 100644 index 000000000..d0ebd06c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 254 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 255 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 254 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 10100010 -37 -20019 -7626 255 1 1010 1010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 11111001 10011101 -37 -20025 -7629 254 0 1001 1001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 11111000 10011000 -37 -20031 -7632 255 1 1000 1000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 11110111 10010011 -37 -20037 -7635 254 0 0111 0111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 11110110 10001110 -37 -20043 -7638 255 1 0110 0110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 11110101 10001001 -37 -20049 -7641 254 0 0101 0101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 11110100 10000100 -37 -20055 -7644 255 1 0100 0100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 11110011 01111111 -37 -20061 -7647 254 0 0011 0011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 11110010 01111010 -37 -20067 -7650 255 1 0010 0010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 11110001 01110101 -37 -20073 -7653 254 0 0001 0001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 11110000 01110000 -37 -20079 -7656 255 1 0000 0000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 11101111 01101011 -37 -20085 -7659 254 0 1111 1111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 11101110 01100110 -37 -20091 -7662 255 1 1110 1110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 11101101 01100001 -37 -20097 -7665 254 0 1101 1101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 11101100 01011100 -37 -20103 -7668 255 1 1100 1100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 11101011 01010111 -37 -20109 -7671 254 0 1011 1011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 11101010 01010010 -37 -20115 -7674 255 1 1010 1010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 11101001 01001101 -37 -20121 -7677 254 0 1001 1001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 11101000 01001000 -37 -20127 -7680 255 1 1000 1000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 11100111 01000011 -37 -20133 -7683 254 0 0111 0111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 11100110 00111110 -37 -20139 -7686 255 1 0110 0110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 11100101 00111001 -37 -20145 -7689 254 0 0101 0101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 11100100 00110100 -37 -20151 -7692 255 1 0100 0100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 11100011 00101111 -37 -20157 -7695 254 0 0011 0011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 11100010 00101010 -37 -20163 -7698 255 1 0010 0010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 11100001 00100101 -37 -20169 -7701 254 0 0001 0001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 11100000 00100000 -37 -20175 -7704 255 1 0000 0000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 11011111 00011011 -37 -20181 -7707 254 0 1111 1111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 11011110 00010110 -37 -20187 -7710 255 1 1110 1110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 11011101 00010001 -37 -20193 -7713 254 0 1101 1101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 11011100 00001100 -37 -20199 -7716 255 1 1100 1100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 11011011 00000111 -37 -20205 -7719 254 0 1011 1011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 11011010 00000010 -37 -20211 -7722 255 1 1010 1010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 11011001 11111101 -37 -20217 -7725 254 0 1001 1001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 11011000 11111000 -37 -20223 -7728 255 1 1000 1000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 11010111 11110011 -37 -20229 -7731 254 0 0111 0111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 255 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log new file mode 100644 index 000000000..299c670c9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : -2 4294967294 11111110 11111110 11111110 at 17 ns +Display : -4 4294967292 11111100 11111100 11111100 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : -13 4294967283 11110011 11110011 11110011 at 28 ns +Display : -4 4294967292 11111100 11111100 11111100 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : -24 4294967272 11101000 11101000 11101000 at 39 ns +Display : -4 4294967292 11111100 11111100 11111100 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : -35 4294967261 11011101 11011101 11011101 at 50 ns +Display : -4 4294967292 11111100 11111100 11111100 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : -46 4294967250 11010010 11010010 11010010 at 61 ns +Display : -4 4294967292 11111100 11111100 11111100 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : -57 4294967239 11000111 11000111 11000111 at 72 ns +Display : -4 4294967292 11111100 11111100 11111100 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : -68 4294967228 10111100 10111100 10111100 at 83 ns +Display : -4 4294967292 11111100 11111100 11111100 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : -79 4294967217 10110001 10110001 10110001 at 94 ns +Display : -4 4294967292 11111100 11111100 11111100 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : -90 4294967206 10100110 10100110 10100110 at 105 ns +Display : -4 4294967292 11111100 11111100 11111100 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : -101 4294967195 10011011 10011011 10011011 at 116 ns +Display : -4 4294967292 11111100 11111100 11111100 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : -112 4294967184 10010000 10010000 10010000 at 127 ns +Display : -4 4294967292 11111100 11111100 11111100 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : -123 4294967173 10000101 10000101 10000101 at 138 ns +Display : -4 4294967292 11111100 11111100 11111100 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp new file mode 100644 index 000000000..1a4d8f4e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "not_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + not_1 not1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp new file mode 100644 index 000000000..a96e400e5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + not_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "not_1.h" + +void not_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = ~ tmp1 ; + tmp2 = ~ tmp2 ; + tmp3 = ~ tmp3 ; + tmp4 = ~ tmp4 ; + tmp5 = ~ tmp5 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 = ~(0x03); + tmp2 = ~(0x03); + tmp3 = ~(tmp3_tmp); + tmp4 = ~(0x03); + tmp5 = ~(0x03); + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f new file mode 100644 index 000000000..07b7b0d72 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f @@ -0,0 +1,4 @@ +not_1/display.cpp +not_1/main.cpp +not_1/not_1.cpp +not_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h new file mode 100644 index 000000000..7366fd3c8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + not_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( not_1 ) +{ + SC_HAS_PROCESS( not_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + not_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp new file mode 100644 index 000000000..eeacba45c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp @@ -0,0 +1,123 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + int tmp7[2]; + char tmp8[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmp7[0] = 12; + tmp7[1] = 0; + tmp8[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmp8[0] = in_value7.read(); + + out_ack.write(true); + + //execute mixed data type or operations + + // signed(8) <- signed(8) & unsigned(8) + tmp1r = tmp1 | tmp2; + // unsigned(8) <- char & long + tmp2r = tmp6 | tmp3; + // long <- int & char + tmp3r = tmp4 | tmp6; + // int <- int & short + tmp4r = tmp4 | tmp5; + // short <- short & const + tmp5r = tmp5 | 5; + // char <- char_array[0] & int_array[1] + tmp6r = tmp8[0] | tmp7[1]; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f new file mode 100644 index 000000000..c767ce1c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/datatypes.cpp +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h new file mode 100644 index 000000000..3332046ad --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h @@ -0,0 +1,127 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp new file mode 100644 index 000000000..258461c24 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h new file mode 100644 index 000000000..3c2ece81a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h @@ -0,0 +1,88 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log 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20480 $ ‘ +Display: 11110111 11111110 -123212 -106832 20485 ‘ +Stimuli: -9 83 12346083 -123213 20486 $ ’ +Display: 11110111 11100111 -123209 -106825 20487 ’ +Stimuli: -7 84 12346088 -123210 20492 $ “ +Display: 11111101 11101100 -123210 -106818 20493 “ +Stimuli: -5 85 12346093 -123207 20498 $ ” +Display: 11111111 11101101 -123203 -106821 20503 ” +Stimuli: -3 86 12346098 -123204 20504 $ • +Display: 11111111 11110110 -123204 -106820 20509 • +Stimuli: -1 87 12346103 -123201 20510 $ – +Display: 11111111 11110111 -123201 -106817 20511 – +Stimuli: 1 88 12346108 -123198 20516 $ — +Display: 01011001 11111100 -123162 -106778 20517 — +Stimuli: 3 89 12346113 -123195 20522 $ ˜ +Display: 01011011 00100101 -123163 -106769 20527 ˜ +Stimuli: 5 90 12346118 -123192 20528 $ ™ +Display: 01011111 00100110 -123156 -106760 20533 ™ +Stimuli: 7 91 12346123 -123189 20534 $ š +Display: 01011111 00101111 -123153 -106753 20535 š +Stimuli: 9 92 12346128 -123186 20540 $ › +Display: 01011101 00110100 -123154 -106754 20541 › +Stimuli: 11 93 12346133 -123183 20546 $ œ +Display: 01011111 00110101 -123147 -106797 20551 œ +Stimuli: 13 94 12346138 -123180 20552 $ +Display: 01011111 00111110 -123148 -106788 20557 +Stimuli: 15 95 12346143 -123177 20558 $ ž +Display: 01011111 00111111 -123145 -106785 20559 ž +Stimuli: 17 96 12346148 -123174 20564 $ Ÿ +Display: 01110001 00100100 -123138 -106786 20565 Ÿ +Stimuli: 19 97 12346153 -123171 20570 $ +Display: 01110011 00101101 -123139 -106785 20575 +Stimuli: 21 98 12346158 -123168 20576 $ ¡ +Display: 01110111 00101110 -123164 -106784 20581 ¡ +Stimuli: 23 99 12346163 -123165 20582 $ ¢ +Display: 01110111 00110111 -123161 -106777 20583 ¢ +Stimuli: 25 100 12346168 -123162 20588 $ £ +Display: 01111101 00111100 -123162 -106770 20589 £ +Stimuli: 27 101 12346173 -123159 20594 $ ¤ +Display: 01111111 00111101 -123155 -106757 20599 ¤ +Stimuli: 29 102 12346178 -123156 20600 $ ¥ + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp new file mode 100644 index 000000000..319d97eb5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Stan Liao, Synopsys, Inc., 1999-10-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + input_valid = 0; + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp new file mode 100644 index 000000000..aff6ff983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h new file mode 100644 index 000000000..fbb96b57b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log new file mode 100644 index 000000000..d5f651425 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 31 31 00001111 00011111 00011111 at 17 ns +Display : 31 31 00001111 00011111 00011111 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 31 31 00001111 00011111 00011111 at 28 ns +Display : 31 31 00001111 00011111 00011111 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 31 31 00011111 00011111 00011111 at 39 ns +Display : 31 31 00011111 00011111 00011111 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 63 00101111 00111111 00111111 at 50 ns +Display : 63 63 00101111 00111111 00111111 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 63 63 00101111 00111111 00111111 at 61 ns +Display : 63 63 00101111 00111111 00111111 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 63 63 00111111 00111111 00111111 at 72 ns +Display : 63 63 00111111 00111111 00111111 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 95 95 01001111 01011111 01011111 at 83 ns +Display : 95 95 01001111 01011111 01011111 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 95 95 01001111 01011111 01011111 at 94 ns +Display : 95 95 01001111 01011111 01011111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 95 95 01011111 01011111 01011111 at 105 ns +Display : 95 95 01011111 01011111 01011111 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 127 127 01101111 01111111 01111111 at 116 ns +Display : 127 127 01101111 01111111 01111111 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 127 127 01101111 01111111 01111111 at 127 ns +Display : 127 127 01101111 01111111 01111111 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 127 127 01111111 01111111 01111111 at 138 ns +Display : 127 127 01111111 01111111 01111111 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp new file mode 100644 index 000000000..fb587275d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "or_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + or_1 or1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp new file mode 100644 index 000000000..e65fdbaf1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "or_1.h" + +void or_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 | 0x0f | 0x12; + tmp2 = tmp2 | 0x0f | 0x13 ; + tmp3 = tmp3 | tmp3_tmp; + tmp4 = tmp4 | 0x0f | 0x14 ; + tmp5 = tmp5 | 0x0f | 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 |= 0x03; + tmp2 |= 0x03; + tmp3 |= tmp3_tmp; + tmp4 |= 0x03; + tmp5 |= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f new file mode 100644 index 000000000..8b7bff4d2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f @@ -0,0 +1,4 @@ +or_1/display.cpp +or_1/main.cpp +or_1/or_1.cpp +or_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h new file mode 100644 index 000000000..99285a543 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( or_1 ) +{ + SC_HAS_PROCESS( or_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + or_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp new file mode 100644 index 000000000..7cb14c66c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "bitwidth.h" + +void bitwidth::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<4> tmp2; + sc_bigint<6> tmp3; + sc_biguint<6> tmp4; + sc_bigint<8> tmp5; + sc_biguint<8> tmp6; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + //execute simple operations + // expected bitwidth 4 4 4 signed + tmp1 = tmp1 << tmp2; + // expected bitwidth 4 6 6 signed + tmp3 = tmp1 << tmp2; + // expected bitwidth 4 4 6 signed + tmp6 = tmp2 << tmp6; + // expected bitwidth 8 8 6 signed + tmp4 = tmp5 << tmp6; + // expected bitwidth 6 8 4 unsigned + tmp2 = tmp4 << tmp6; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f new file mode 100644 index 000000000..53a59162e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f @@ -0,0 +1,4 @@ +bitwidth/stimulus.cpp +bitwidth/display.cpp +bitwidth/bitwidth.cpp +bitwidth/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h new file mode 100644 index 000000000..e088b3a4a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h @@ -0,0 +1,121 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( bitwidth ) +{ + SC_HAS_PROCESS( bitwidth ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector6& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal_bool_vector8& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector6& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal_bool_vector8& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + bitwidth ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector6& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal_bool_vector8& IN_VALUE6, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector6& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal_bool_vector8& OUT_VALUE6, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h new file mode 100644 index 000000000..2a49981d9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp new file mode 100644 index 000000000..17eba10b1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << in_data6.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 12) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h new file mode 100644 index 000000000..922ed13a9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector6& in_data3; // Input port + const sc_signal_bool_vector6& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal_bool_vector8& in_data6; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector4& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector6& IN_DATA3, + const sc_signal_bool_vector6& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal_bool_vector8& IN_DATA6, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_data6(IN_DATA6), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log new file mode 100644 index 000000000..ad7d0b4fd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log @@ -0,0 +1,27 @@ +SystemC Simulation +Stimuli : 1 1 1 1 1 1 at 23 ns +Display : 0010 0000 000100 000100 00000001 00000010 at 27 ns +Stimuli : 3 3 3 3 3 3 at 44 ns +Display : 1000 0000 000000 000000 00000011 00011000 at 48 ns +Stimuli : 5 5 5 5 5 5 at 65 ns +Display : 0000 0000 000000 000000 00000101 10100000 at 69 ns +Stimuli : 7 7 7 7 7 7 at 86 ns +Display : 0000 0000 000000 000000 00000111 10000000 at 90 ns +Stimuli : -7 9 9 9 9 9 at 107 ns +Display : 0000 1001 000000 001001 00001001 00000000 at 111 ns +Stimuli : -5 11 11 11 11 11 at 128 ns +Display : 0000 1011 000000 001011 00001011 00000000 at 132 ns +Stimuli : -3 13 13 13 13 13 at 149 ns +Display : 0000 1101 000000 001101 00001101 00000000 at 153 ns +Stimuli : -1 15 15 15 15 15 at 170 ns +Display : 0000 1111 000000 001111 00001111 00000000 at 174 ns +Stimuli : 1 1 17 17 17 17 at 191 ns +Display : 0010 0001 000100 010001 00010001 00000000 at 195 ns +Stimuli : 3 3 19 19 19 19 at 212 ns +Display : 1000 0011 000000 010011 00010011 00000000 at 216 ns +Stimuli : 5 5 21 21 21 21 at 233 ns +Display : 0000 0101 000000 010101 00010101 00000000 at 237 ns +Stimuli : 7 7 23 23 23 23 at 254 ns +Display : 0000 0111 000000 010111 00010111 00000000 at 258 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp new file mode 100644 index 000000000..8a7ff91be --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "bitwidth.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector6 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal_bool_vector8 stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector6 result_line4; + sc_signal_bool_vector8 result_line5; + sc_signal_bool_vector8 result_line6; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid); + + bitwidth bitwidth1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp new file mode 100644 index 000000000..3d7567c14 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + sc_signed send_value1(4); + sc_unsigned send_value2(4); + sc_signed send_value3(6); + sc_unsigned send_value4(6); + sc_signed send_value5(8); + sc_unsigned send_value6(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value1 = 1; + send_value2 = 1; + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + send_value6 = 1; + out_stimulus1.write(1); + out_stimulus2.write(1); + out_stimulus3.write(1); + out_stimulus4.write(1); + out_stimulus5.write(1); + out_stimulus6.write(1); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_stimulus6.write( send_value6 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " + << send_value6 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+2; + send_value2 = send_value2+2; + send_value3 = send_value3+2; + send_value4 = send_value4+2; + send_value5 = send_value5+2; + send_value6 = send_value6+2; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h new file mode 100644 index 000000000..fa0b64302 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector6& out_stimulus3; + sc_signal_bool_vector6& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal_bool_vector8& out_stimulus6; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector6& OUT_STIMULUS3, + sc_signal_bool_vector6& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal_bool_vector8& OUT_STIMULUS6, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_stimulus6(OUT_STIMULUS6), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp new file mode 100644 index 000000000..67ed1a1ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" +#define true 1 +#define false 0 + +void datatypes::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << 2; + tmp3r = tmp3 << 1; + tmp4r = tmp4 << (tmp7[1] % 16); + tmp5r = tmp3 << ((unsigned int)(tmp1.to_int()) % 32); + tmp6r = tmp6 << 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << (unsigned int)(tmp4 % 8); + tmp3r = tmp3 << (short)(tmp5 % 32); + tmp4r = tmp4 << 2; + tmp5r = tmp3 << ((unsigned int)(tmp5) % 16); + tmp6r = tmp6 << (tmp2.to_uint() % 32); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h new file mode 100644 index 000000000..6def13c41 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp new file mode 100644 index 000000000..15e132440 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << (int)in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log 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0 94 +Stimuli: 57 95 95 93 20094 +Display: 11001000 01111100 190 380928 0 96 +Stimuli: 58 96 96 94 20095 +Display: 11010000 10000000 192 385024 0 98 +Stimuli: 59 97 97 95 20096 +Display: 11011000 10000100 194 389120 0 100 +Stimuli: 60 98 98 96 20097 +Display: 11100000 10001000 196 393216 0 102 +Stimuli: 61 99 99 97 20098 +Display: 11101000 10001100 198 397312 0 104 +Stimuli: 62 100 100 98 20099 +Display: 11110000 10010000 200 401408 0 106 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp new file mode 100644 index 000000000..813f5f29d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp new file mode 100644 index 000000000..79d2a0f86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log Binary files differnew file mode 100644 index 000000000..9666885d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp new file mode 100644 index 000000000..ffb011ab2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + sharing sharing1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp new file mode 100644 index 000000000..392ac6ca5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "sharing.h" +#define true 1 +#define false 0 + +void sharing::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type shit left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << 2; + tmp3r = tmp3 << 1; + tmp4r = tmp4 << (tmp7[1] % 32); + tmp5r = tmp3 << ((unsigned int)tmp1.to_int() % 32); + tmp6r = tmp6 << 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << (tmp4 % 8); + tmp3r = tmp3 << (tmp5 % 32); + tmp4r = tmp4 << 2; + tmp5r = tmp3 << ((unsigned int)(tmp5) % 32); + tmp6r = tmp6 << (tmp2.to_uint() % 8); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f new file mode 100644 index 000000000..998e0f309 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/display.cpp +sharing/main.cpp +sharing/sharing.cpp +sharing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h new file mode 100644 index 000000000..5552db43a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp new file mode 100644 index 000000000..79d2a0f86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log new file mode 100644 index 000000000..acc069982 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11111011 00000000 0 -1 0 ) +Stimuli: -36 2 2 0 20001 +Display: 11111011 00000000 1 0 0 ) +Stimuli: -35 3 3 1 20002 +Display: 11111011 00000000 1 0 0 * +Stimuli: -34 4 4 2 20003 +Display: 11111011 00000001 2 0 0 * +Stimuli: -33 5 5 3 20004 +Display: 11111011 00000001 2 0 0 + +Stimuli: -32 6 6 4 20005 +Display: 11111100 00000001 3 0 6 + +Stimuli: -31 7 7 5 20006 +Display: 11111100 00000001 3 0 3 , +Stimuli: -30 8 8 6 20007 +Display: 11111100 00000010 4 0 2 , +Stimuli: -29 9 9 7 20008 +Display: 11111100 00000010 4 0 1 - +Stimuli: -28 10 10 8 20009 +Display: 11111100 00000010 5 1 0 - +Stimuli: -27 11 11 9 20010 +Display: 11111100 00000010 5 1 0 . +Stimuli: -26 12 12 10 20011 +Display: 11111100 00000011 6 1 0 . +Stimuli: -25 13 13 11 20012 +Display: 11111100 00000011 6 1 0 / +Stimuli: -24 14 14 12 20013 +Display: 11111101 00000011 7 1 0 / +Stimuli: -23 15 15 13 20014 +Display: 11111101 00000011 7 1 0 0 +Stimuli: -22 16 16 14 20015 +Display: 11111101 00000100 8 1 0 0 +Stimuli: -21 17 17 15 20016 +Display: 11111101 00000100 8 1 0 1 +Stimuli: -20 18 18 16 20017 +Display: 11111101 00000100 9 2 0 1 +Stimuli: -19 19 19 17 20018 +Display: 11111101 00000100 9 2 0 2 +Stimuli: -18 20 20 18 20019 +Display: 11111101 00000101 10 2 0 2 +Stimuli: -17 21 21 19 20020 +Display: 11111101 00000101 10 2 0 3 +Stimuli: -16 22 22 20 20021 +Display: 11111110 00000101 11 2 0 3 +Stimuli: -15 23 23 21 20022 +Display: 11111110 00000101 11 2 0 4 +Stimuli: -14 24 24 22 20023 +Display: 11111110 00000110 12 2 0 4 +Stimuli: -13 25 25 23 20024 +Display: 11111110 00000110 12 2 0 5 +Stimuli: -12 26 26 24 20025 +Display: 11111110 00000110 13 3 0 5 +Stimuli: -11 27 27 25 20026 +Display: 11111110 00000110 13 3 0 6 +Stimuli: -10 28 28 26 20027 +Display: 11111110 00000111 14 3 0 6 +Stimuli: -9 29 29 27 20028 +Display: 11111110 00000111 14 3 0 7 +Stimuli: -8 30 30 28 20029 +Display: 11111111 00000111 15 3 0 7 +Stimuli: -7 31 31 29 20030 +Display: 11111111 00000111 15 3 0 8 +Stimuli: -6 32 32 30 20031 +Display: 11111111 00001000 16 3 0 8 +Stimuli: -5 33 33 31 20032 +Display: 11111111 00001000 16 3 0 9 +Stimuli: -4 34 34 32 20033 +Display: 11111111 00001000 17 4 0 9 +Stimuli: -3 35 35 33 20034 +Display: 11111111 00001000 17 4 0 : +Stimuli: -2 36 36 34 20035 +Display: 11111111 00001001 18 4 0 : +Stimuli: -1 37 37 35 20036 +Display: 11111111 00001001 18 4 0 ; +Stimuli: 0 38 38 36 20037 +Display: 00000000 00001001 19 4 38 ; +Stimuli: 1 39 39 37 20038 +Display: 00000000 00001001 19 4 19 < +Stimuli: 2 40 40 38 20039 +Display: 00000000 00001010 20 4 10 < +Stimuli: 3 41 41 39 20040 +Display: 00000000 00001010 20 4 5 = +Stimuli: 4 42 42 40 20041 +Display: 00000000 00001010 21 5 2 = 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+Display: 00000010 00001110 29 7 0 Å +Stimuli: 21 59 59 57 20058 +Display: 00000010 00001110 29 7 0 Æ +Stimuli: 22 60 60 58 20059 +Display: 00000010 00001111 30 7 0 Æ +Stimuli: 23 61 61 59 20060 +Display: 00000010 00001111 30 7 0 Ç +Stimuli: 24 62 62 60 20061 +Display: 00000011 00001111 31 7 0 Ç +Stimuli: 25 63 63 61 20062 +Display: 00000011 00001111 31 7 0 È +Stimuli: 26 64 64 62 20063 +Display: 00000011 00010000 32 7 0 È +Stimuli: 27 65 65 63 20064 +Display: 00000011 00010000 32 7 0 É +Stimuli: 28 66 66 64 20065 +Display: 00000011 00010000 33 8 0 É +Stimuli: 29 67 67 65 20066 +Display: 00000011 00010000 33 8 0 Ê +Stimuli: 30 68 68 66 20067 +Display: 00000011 00010001 34 8 0 Ê +Stimuli: 31 69 69 67 20068 +Display: 00000011 00010001 34 8 0 Ë +Stimuli: 32 70 70 68 20069 +Display: 00000100 00010001 35 8 70 Ë +Stimuli: 33 71 71 69 20070 +Display: 00000100 00010001 35 8 35 Ì +Stimuli: 34 72 72 70 20071 +Display: 00000100 00010010 36 8 18 Ì +Stimuli: 35 73 73 71 20072 +Display: 00000100 00010010 36 8 9 Í +Stimuli: 36 74 74 72 20073 +Display: 00000100 00010010 37 9 4 Í +Stimuli: 37 75 75 73 20074 +Display: 00000100 00010010 37 9 2 Î +Stimuli: 38 76 76 74 20075 +Display: 00000100 00010011 38 9 1 Î +Stimuli: 39 77 77 75 20076 +Display: 00000100 00010011 38 9 0 Ï +Stimuli: 40 78 78 76 20077 +Display: 00000101 00010011 39 9 0 Ï +Stimuli: 41 79 79 77 20078 +Display: 00000101 00010011 39 9 0 Ð +Stimuli: 42 80 80 78 20079 +Display: 00000101 00010100 40 9 0 Ð +Stimuli: 43 81 81 79 20080 +Display: 00000101 00010100 40 9 0 Ñ +Stimuli: 44 82 82 80 20081 +Display: 00000101 00010100 41 10 0 Ñ +Stimuli: 45 83 83 81 20082 +Display: 00000101 00010100 41 10 0 Ò +Stimuli: 46 84 84 82 20083 +Display: 00000101 00010101 42 10 0 Ò +Stimuli: 47 85 85 83 20084 +Display: 00000101 00010101 42 10 0 Ó +Stimuli: 48 86 86 84 20085 +Display: 00000110 00010101 43 10 0 Ó +Stimuli: 49 87 87 85 20086 +Display: 00000110 00010101 43 10 0 Ô +Stimuli: 50 88 88 86 20087 +Display: 00000110 00010110 44 10 0 Ô +Stimuli: 51 89 89 87 20088 +Display: 00000110 00010110 44 10 0 Õ +Stimuli: 52 90 90 88 20089 +Display: 00000110 00010110 45 11 0 Õ +Stimuli: 53 91 91 89 20090 +Display: 00000110 00010110 45 11 0 Ö +Stimuli: 54 92 92 90 20091 +Display: 00000110 00010111 46 11 0 Ö +Stimuli: 55 93 93 91 20092 +Display: 00000110 00010111 46 11 0 × +Stimuli: 56 94 94 92 20093 +Display: 00000111 00010111 47 11 0 × +Stimuli: 57 95 95 93 20094 +Display: 00000111 00010111 47 11 0 Ø +Stimuli: 58 96 96 94 20095 +Display: 00000111 00011000 48 11 0 Ø +Stimuli: 59 97 97 95 20096 +Display: 00000111 00011000 48 11 0 Ù +Stimuli: 60 98 98 96 20097 +Display: 00000111 00011000 49 12 0 Ù +Stimuli: 61 99 99 97 20098 +Display: 00000111 00011000 49 12 0 Ú +Stimuli: 62 100 100 98 20099 +Display: 00000111 00011001 50 12 0 Ú + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 new file mode 100644 index 000000000..7faa47515 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11111011 00000000 0 -1 0 ) +Stimuli: -36 2 2 0 20001 +Display: 11111011 00000000 1 0 0 ) +Stimuli: -35 3 3 1 20002 +Display: 11111011 00000000 1 0 0 * +Stimuli: -34 4 4 2 20003 +Display: 11111011 00000001 2 0 0 * +Stimuli: -33 5 5 3 20004 +Display: 11111011 00000001 2 0 0 + +Stimuli: -32 6 6 4 20005 +Display: 11111100 00000001 3 0 6 + +Stimuli: -31 7 7 5 20006 +Display: 11111100 00000001 3 0 3 , +Stimuli: -30 8 8 6 20007 +Display: 11111100 00000010 4 0 2 , +Stimuli: -29 9 9 7 20008 +Display: 11111100 00000010 4 0 1 - +Stimuli: -28 10 10 8 20009 +Display: 11111100 00000010 5 1 0 - +Stimuli: -27 11 11 9 20010 +Display: 11111100 00000010 5 1 0 . +Stimuli: -26 12 12 10 20011 +Display: 11111100 00000011 6 1 0 . +Stimuli: -25 13 13 11 20012 +Display: 11111100 00000011 6 1 0 / +Stimuli: -24 14 14 12 20013 +Display: 11111101 00000011 7 1 0 / +Stimuli: -23 15 15 13 20014 +Display: 11111101 00000011 7 1 0 0 +Stimuli: -22 16 16 14 20015 +Display: 11111101 00000100 8 1 0 0 +Stimuli: -21 17 17 15 20016 +Display: 11111101 00000100 8 1 0 1 +Stimuli: -20 18 18 16 20017 +Display: 11111101 00000100 9 2 0 1 +Stimuli: -19 19 19 17 20018 +Display: 11111101 00000100 9 2 0 2 +Stimuli: -18 20 20 18 20019 +Display: 11111101 00000101 10 2 0 2 +Stimuli: -17 21 21 19 20020 +Display: 11111101 00000101 10 2 0 3 +Stimuli: -16 22 22 20 20021 +Display: 11111110 00000101 11 2 0 3 +Stimuli: -15 23 23 21 20022 +Display: 11111110 00000101 11 2 0 4 +Stimuli: -14 24 24 22 20023 +Display: 11111110 00000110 12 2 0 4 +Stimuli: -13 25 25 23 20024 +Display: 11111110 00000110 12 2 0 5 +Stimuli: -12 26 26 24 20025 +Display: 11111110 00000110 13 3 0 5 +Stimuli: -11 27 27 25 20026 +Display: 11111110 00000110 13 3 0 6 +Stimuli: -10 28 28 26 20027 +Display: 11111110 00000111 14 3 0 6 +Stimuli: -9 29 29 27 20028 +Display: 11111110 00000111 14 3 0 7 +Stimuli: -8 30 30 28 20029 +Display: 11111111 00000111 15 3 0 7 +Stimuli: -7 31 31 29 20030 +Display: 11111111 00000111 15 3 0 8 +Stimuli: -6 32 32 30 20031 +Display: 11111111 00001000 16 3 0 8 +Stimuli: -5 33 33 31 20032 +Display: 11111111 00001000 16 3 0 9 +Stimuli: -4 34 34 32 20033 +Display: 11111111 00001000 17 4 0 9 +Stimuli: -3 35 35 33 20034 +Display: 11111111 00001000 17 4 0 : +Stimuli: -2 36 36 34 20035 +Display: 11111111 00001001 18 4 0 : +Stimuli: -1 37 37 35 20036 +Display: 11111111 00001001 18 4 0 ; +Stimuli: 0 38 38 36 20037 +Display: 00000000 00001001 19 4 38 ; +Stimuli: 1 39 39 37 20038 +Display: 00000000 00001001 19 4 19 < +Stimuli: 2 40 40 38 20039 +Display: 00000000 00001010 20 4 10 < +Stimuli: 3 41 41 39 20040 +Display: 00000000 00001010 20 4 5 = +Stimuli: 4 42 42 40 20041 +Display: 00000000 00001010 21 5 2 = +Stimuli: 5 43 43 41 20042 +Display: 00000000 00001010 21 5 1 > +Stimuli: 6 44 44 42 20043 +Display: 00000000 00001011 22 5 0 > +Stimuli: 7 45 45 43 20044 +Display: 00000000 00001011 22 5 0 ? +Stimuli: 8 46 46 44 20045 +Display: 00000001 00001011 23 5 0 ? +Stimuli: 9 47 47 45 20046 +Display: 00000001 00001011 23 5 0 @ +Stimuli: 10 48 48 46 20047 +Display: 00000001 00001100 24 5 0 @ +Stimuli: 11 49 49 47 20048 +Display: 00000001 00001100 24 5 0 A +Stimuli: 12 50 50 48 20049 +Display: 00000001 00001100 25 6 0 A +Stimuli: 13 51 51 49 20050 +Display: 00000001 00001100 25 6 0 B +Stimuli: 14 52 52 50 20051 +Display: 00000001 00001101 26 6 0 B +Stimuli: 15 53 53 51 20052 +Display: 00000001 00001101 26 6 0 C +Stimuli: 16 54 54 52 20053 +Display: 00000010 00001101 27 6 0 C +Stimuli: 17 55 55 53 20054 +Display: 00000010 00001101 27 6 0 D +Stimuli: 18 56 56 54 20055 +Display: 00000010 00001110 28 6 0 D +Stimuli: 19 57 57 55 20056 +Display: 00000010 00001110 28 6 0 E +Stimuli: 20 58 58 56 20057 +Display: 00000010 00001110 29 7 0 E +Stimuli: 21 59 59 57 20058 +Display: 00000010 00001110 29 7 0 F +Stimuli: 22 60 60 58 20059 +Display: 00000010 00001111 30 7 0 F +Stimuli: 23 61 61 59 20060 +Display: 00000010 00001111 30 7 0 G +Stimuli: 24 62 62 60 20061 +Display: 00000011 00001111 31 7 0 G +Stimuli: 25 63 63 61 20062 +Display: 00000011 00001111 31 7 0 H +Stimuli: 26 64 64 62 20063 +Display: 00000011 00010000 32 7 0 H +Stimuli: 27 65 65 63 20064 +Display: 00000011 00010000 32 7 0 I +Stimuli: 28 66 66 64 20065 +Display: 00000011 00010000 33 8 0 I +Stimuli: 29 67 67 65 20066 +Display: 00000011 00010000 33 8 0 J +Stimuli: 30 68 68 66 20067 +Display: 00000011 00010001 34 8 0 J +Stimuli: 31 69 69 67 20068 +Display: 00000011 00010001 34 8 0 K +Stimuli: 32 70 70 68 20069 +Display: 00000100 00010001 35 8 70 K +Stimuli: 33 71 71 69 20070 +Display: 00000100 00010001 35 8 35 L +Stimuli: 34 72 72 70 20071 +Display: 00000100 00010010 36 8 18 L +Stimuli: 35 73 73 71 20072 +Display: 00000100 00010010 36 8 9 M +Stimuli: 36 74 74 72 20073 +Display: 00000100 00010010 37 9 4 M +Stimuli: 37 75 75 73 20074 +Display: 00000100 00010010 37 9 2 N +Stimuli: 38 76 76 74 20075 +Display: 00000100 00010011 38 9 1 N +Stimuli: 39 77 77 75 20076 +Display: 00000100 00010011 38 9 0 O +Stimuli: 40 78 78 76 20077 +Display: 00000101 00010011 39 9 0 O +Stimuli: 41 79 79 77 20078 +Display: 00000101 00010011 39 9 0 P +Stimuli: 42 80 80 78 20079 +Display: 00000101 00010100 40 9 0 P +Stimuli: 43 81 81 79 20080 +Display: 00000101 00010100 40 9 0 Q +Stimuli: 44 82 82 80 20081 +Display: 00000101 00010100 41 10 0 Q +Stimuli: 45 83 83 81 20082 +Display: 00000101 00010100 41 10 0 R +Stimuli: 46 84 84 82 20083 +Display: 00000101 00010101 42 10 0 R +Stimuli: 47 85 85 83 20084 +Display: 00000101 00010101 42 10 0 S +Stimuli: 48 86 86 84 20085 +Display: 00000110 00010101 43 10 0 S +Stimuli: 49 87 87 85 20086 +Display: 00000110 00010101 43 10 0 T +Stimuli: 50 88 88 86 20087 +Display: 00000110 00010110 44 10 0 T +Stimuli: 51 89 89 87 20088 +Display: 00000110 00010110 44 10 0 U +Stimuli: 52 90 90 88 20089 +Display: 00000110 00010110 45 11 0 U +Stimuli: 53 91 91 89 20090 +Display: 00000110 00010110 45 11 0 V +Stimuli: 54 92 92 90 20091 +Display: 00000110 00010111 46 11 0 V +Stimuli: 55 93 93 91 20092 +Display: 00000110 00010111 46 11 0 W +Stimuli: 56 94 94 92 20093 +Display: 00000111 00010111 47 11 0 W +Stimuli: 57 95 95 93 20094 +Display: 00000111 00010111 47 11 0 X +Stimuli: 58 96 96 94 20095 +Display: 00000111 00011000 48 11 0 X +Stimuli: 59 97 97 95 20096 +Display: 00000111 00011000 48 11 0 Y +Stimuli: 60 98 98 96 20097 +Display: 00000111 00011000 49 12 0 Y +Stimuli: 61 99 99 97 20098 +Display: 00000111 00011000 49 12 0 Z +Stimuli: 62 100 100 98 20099 +Display: 00000111 00011001 50 12 0 Z + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp new file mode 100644 index 000000000..ffb011ab2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + sharing sharing1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp new file mode 100644 index 000000000..2b1dc2eb4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "sharing.h" +#define true 1 +#define false 0 + +void sharing::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type addition operations + tmp1r = tmp1 >> (tmp7[0] % 9); + tmp2r = tmp2 >> 2; + tmp3r = tmp3 >> 1; + tmp4r = tmp4 >> (tmp7[1] % 9); + tmp5r = tmp3 >> (((unsigned int)tmp1.to_int()) % 32); + tmp6r = tmp6 >> 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type addition operations + tmp1r = tmp1 >> (tmp7[0] % 9); + tmp2r = tmp2 >> (tmp4 % 9); + tmp3r = tmp3 >> (tmp5 % 33); + tmp4r = tmp4 >> 2; + tmp5r = tmp3 >> (((unsigned int)tmp5) % 33); + tmp6r = tmp6 >> (tmp2.to_uint() % 9); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f new file mode 100644 index 000000000..998e0f309 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/display.cpp +sharing/main.cpp +sharing/sharing.cpp +sharing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h new file mode 100644 index 000000000..5552db43a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp new file mode 100644 index 000000000..5b863a7ed --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp @@ -0,0 +1,142 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type xor operations + + // signed(8) <- signed(8) ^ unsigned(8) + tmp1r = tmp1 ^ tmp2; + // unsigned(8) <- char ^ long + tmp2r = tmp6 ^ tmp3; + // long <- int ^ char + tmp3r = tmp4 ^ tmp6; + // int <- int ^ short + tmp4r = tmp4 ^ tmp5; + // short <- short ^ const + tmp5r = tmp5 ^ 5; + // char <- char_array[0] ^ int_array[1] + tmp6r = tmpb[0] ^ tmpa[1]; + // bool <- bool ^ bool; + tmp7r = tmp7 ^ tmp7; + // sc_bool_vector(4) <- sc_bool_vector(4) ^ sc_logic_vector(4) + tmp8r = tmp8 ^ tmp9; + // sc_logic_vector(4) <- sc_bool_vector(4) ^ "0111" + tmp9r = tmp9 ^ sc_bv<4>( "0111" ); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp new file mode 100644 index 000000000..0c6fdf20e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log new file mode 100644 index 000000000..05838b4cf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 01010111 01101010 -123420 -109600 20005 > 0 0011 0101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 01010100 01110111 -123417 -109595 20003 = 0 0001 0100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 01011101 01111100 -123422 -109590 20009 < 0 0111 0011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 01011110 01111001 -123411 -109573 20023 ; 0 0001 0010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 01011011 01000110 -123416 -109580 20029 : 0 0011 0001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 01011000 01000011 -123413 -109583 20027 9 0 0001 0000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 01101001 01001000 -123402 -109674 20033 8 0 1111 1111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 01101010 01010101 -123407 -109665 20047 7 0 0001 1110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 01101111 01010010 -123396 -109688 20053 6 0 0011 1101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 01101100 01011111 -123393 -109683 20051 5 0 0001 1100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 01100101 10100100 -123398 -109694 20057 4 0 0111 1011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 01100110 10100001 -123451 -109693 20071 3 0 0001 1010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 01100011 10101110 -123456 -109684 20077 2 0 0011 1001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 01100000 10101011 -123453 -109687 20075 1 0 0001 1000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 01100001 10110000 -123442 -109666 20081 0 0 1111 0111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 01100010 10111101 -123447 -109673 20095 / 0 0001 0110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 01100111 10111010 -123436 -109712 20101 . 0 0011 0101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 01100100 10000111 -123433 -109707 20099 - 0 0001 0100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 01101101 10001100 -123438 -109702 20105 , 0 0111 0011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 01101110 10001001 -123427 -109717 20119 + 0 0001 0010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 01101011 10010110 -123432 -109724 20125 * 0 0011 0001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 01101000 10010011 -123429 -109727 20123 ) 0 0001 0000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 10011001 10011000 -123354 -110426 20129 ( 0 1111 1111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 10011010 11100101 -123359 -110417 20143 ' 0 0001 1110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 10011111 11100010 -123348 -110408 20149 & 0 0011 1101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 10011100 11101111 -123345 -110403 20147 % 0 0001 1100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 10010101 11110100 -123350 -110414 20153 $ 0 0111 1011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 10010110 11110001 -123339 -110381 20167 # 0 0001 1010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 10010011 11111110 -123344 -110372 20173 " 0 0011 1001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 10010000 11111011 -123341 -110375 20171 ! 0 0001 1000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 10110001 11000000 -123330 -110386 20177 0 1111 0111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 10110010 11001101 -123335 -110393 20191 0 0001 0110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 10110111 11001010 -123388 -110400 20197 0 0011 0101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 10110100 11010111 -123385 -110395 20195 0 0001 0100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 10111101 11011100 -123390 -110390 20201 0 0111 0011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 10111110 11011001 -123379 -110373 20215 0 0001 0010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 10111011 00100110 -123384 -110380 20221 0 0011 0001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 10111000 00100011 -123381 -110383 20219 0 0001 0000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 10001001 00101000 -123370 -110282 20225 0 1111 1111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 10001010 00110101 -123375 -110273 20239 0 0001 1110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h new file mode 100644 index 000000000..cf3a89370 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log new file mode 100644 index 000000000..71803889d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 28 29 00001110 00011010 00011011 at 17 ns +Display : 31 30 00001101 00011001 00011000 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 17 16 00000011 00010111 00010110 at 28 ns +Display : 18 19 00000000 00010100 00010101 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 10 11 00011000 00001100 00001101 at 39 ns +Display : 9 8 00011011 00001111 00001110 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 62 00101101 00111001 00111000 at 50 ns +Display : 60 61 00101110 00111010 00111011 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 48 49 00100010 00110110 00110111 at 61 ns +Display : 51 50 00100001 00110101 00110100 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 37 36 00110111 00100011 00100010 at 72 ns +Display : 38 39 00110100 00100000 00100001 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 94 95 01001100 01011000 01011001 at 83 ns +Display : 93 92 01001111 01011011 01011010 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 83 82 01000001 01010101 01010100 at 94 ns +Display : 80 81 01000010 01010110 01010111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 68 69 01010110 01000010 01000011 at 105 ns +Display : 71 70 01010101 01000001 01000000 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 121 120 01101011 01111111 01111110 at 116 ns +Display : 122 123 01101000 01111100 01111101 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 114 115 01100000 01110100 01110101 at 127 ns +Display : 113 112 01100011 01110111 01110110 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 103 102 01110101 01100001 01100000 at 138 ns +Display : 100 101 01110110 01100010 01100011 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp new file mode 100644 index 000000000..ba25bdac8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "xor_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + xor_1 xor1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp new file mode 100644 index 000000000..623e1b2f9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + xor_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "xor_1.h" + +void xor_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 ^ 0x0f ^ 0x12; + tmp2 = tmp2 ^ 0x0f ^ 0x13 ; + tmp3 = tmp3 ^ tmp3_tmp; + tmp4 = tmp4 ^ 0x0f ^ 0x14 ; + tmp5 = tmp5 ^ 0x0f ^ 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 ^= 0x03; + tmp2 ^= 0x03; + tmp3 ^= tmp3_tmp; + tmp4 ^= 0x03; + tmp5 ^= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f new file mode 100644 index 000000000..aa5cf3860 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f @@ -0,0 +1,4 @@ +xor_1/display.cpp +xor_1/main.cpp +xor_1/stimulus.cpp +xor_1/xor_1.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h new file mode 100644 index 000000000..d56813a54 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + xor_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( xor_1 ) +{ + SC_HAS_PROCESS( xor_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + xor_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF |