diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining')
10 files changed, 657 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp new file mode 100644 index 000000000..0135a0381 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h new file mode 100644 index 000000000..74d4c67ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log new file mode 100644 index 000000000..3a3a8c358 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0000 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0000 0010 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0000 0011 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0100 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0101 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0110 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0111 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp new file mode 100644 index 000000000..08da0e3ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" + +// list of defines +#define clock(a) wait(a) +#define intu4(a) sc_biguint<4> a; +#define vec4(a) sc_lv<4> a; +#define my_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + break; \ + default : \ + b = c; \ + break; \ + }; +#define my_wait_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + wait(); \ + break; \ + default : \ + b = c; \ + wait(); \ + break; \ + }; + +void inlining::entry(){ + + int tmp1; + int tmp2; + vec4(tmp3); + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_valid.write(false); + clock(1); + } else clock(1); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read().to_int(); + tmp2 = in_value2.read().to_int(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //execution + my_wait_case(tmp1, tmp3, tmp4); + out_value1.write(tmp3); + clock(1); + + my_case(tmp2, tmp3, tmp4); + out_value2.write(tmp4); + out_valid.write(true); + clock(1); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f new file mode 100644 index 000000000..fc00870e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f @@ -0,0 +1,4 @@ +inlining/display.cpp +inlining/inlining.cpp +inlining/main.cpp +inlining/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h new file mode 100644 index 000000000..70380e24e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h @@ -0,0 +1,93 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( inlining ) +{ + SC_HAS_PROCESS( inlining ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1 ; + const sc_signal_bool_vector& in_value2 ; + const sc_signal_bool_vector& in_value3 ; + const sc_signal_bool_vector& in_value4 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + inlining( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + // + void entry (); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp new file mode 100644 index 000000000..c859cafce --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal<bool> output_valid; + + + + inlining inlining1 ( + "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid + ); + + display display1 ("display", + clock, + result1, + result2, + output_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp new file mode 100644 index 000000000..c3d3dea5a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h new file mode 100644 index 000000000..058da3946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF |