diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general/control/case')
40 files changed, 3054 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp new file mode 100644 index 000000000..b25ae0fa6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp @@ -0,0 +1,171 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-10-25 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" + + +void balancing::entry(){ + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + unsigned int tmpint; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + out_tmp2 = 0; + out_tmp3 = 0; + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + + //easy, just a bunch of different waits + out_valid1.write(true); + tmpint = tmp1.to_uint(); + switch (tmpint) { + case 4 : + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + case 3 : + out_value1.write(2); + wait(); + wait(); + wait(); + case 2 : + out_value1.write(1); + wait(); + wait(); + default : + out_value1.write(tmp1); + wait(); + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + tmp1 = tmp2; + out_valid2.write(true); + wait(); + tmpint = tmp1.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + wait(); + case 8 | 9 | 10 | 11: + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + }; + wait(); + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp3 = in_value3.read(); + out_valid3.write(true); + wait(); + tmpint = tmp3.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + case 8 : + case 9 : + case 10 : + case 11 : + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + }; + wait(); + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f new file mode 100644 index 000000000..0a6488983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f @@ -0,0 +1,4 @@ +balancing/balancing.cpp +balancing/display.cpp +balancing/main.cpp +balancing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h new file mode 100644 index 000000000..a27e68018 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( balancing ) +{ + SC_HAS_PROCESS( balancing ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + balancing( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp new file mode 100644 index 000000000..55ff8cb26 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up. + while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h new file mode 100644 index 000000000..f42a6b294 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log new file mode 100644 index 000000000..264e09ae0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log @@ -0,0 +1,163 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data2 0000 at 6 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data2 0000 at 9 ns +Display : in_data2 0000 at 10 ns +Display : in_data2 0000 at 11 ns +Display : in_data2 0000 at 12 ns +Display : in_data3 0000 at 14 ns +Display : in_data3 0000 at 15 ns +Display : in_data3 0000 at 16 ns +Display : in_data3 0000 at 17 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data3 0000 at 18 ns +Display : in_data3 0000 at 19 ns +Display : in_data3 0000 at 20 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data1 0010 at 38 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data2 0001 at 42 ns +Display : in_data2 0001 at 43 ns +Display : in_data2 0001 at 44 ns +Display : in_data2 0001 at 45 ns +Display : in_data2 0001 at 46 ns +Display : in_data3 0000 at 48 ns +Display : in_data3 0000 at 49 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data3 0000 at 50 ns +Display : in_data3 0000 at 51 ns +Display : in_data3 0000 at 52 ns +Display : in_data3 0000 at 53 ns +Display : in_data3 0000 at 54 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0011 at 72 ns +Display : in_data1 0010 at 73 ns +Display : in_data1 0010 at 74 ns +Display : in_data1 0010 at 75 ns +Display : in_data1 0001 at 76 ns +Display : in_data1 0001 at 77 ns +Display : in_data1 0100 at 78 ns +Display : in_data2 0001 at 80 ns +Display : in_data2 0001 at 81 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data2 0001 at 82 ns +Display : in_data2 0001 at 83 ns +Display : in_data2 0001 at 84 ns +Display : in_data2 0001 at 85 ns +Display : in_data3 0000 at 87 ns +Display : in_data3 0000 at 88 ns +Display : in_data3 0000 at 89 ns +Display : in_data3 0000 at 90 ns +Display : in_data3 0000 at 91 ns +Display : in_data3 0000 at 92 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0110 at 100 ns +Display : in_data2 0001 at 102 ns +Display : in_data2 0001 at 103 ns +Display : in_data2 0001 at 104 ns +Display : in_data2 0001 at 105 ns +Display : in_data2 0001 at 106 ns +Display : in_data2 0001 at 107 ns +Display : in_data3 0000 at 109 ns +Display : in_data3 0000 at 110 ns +Display : in_data3 0000 at 111 ns +Display : in_data3 0000 at 112 ns +Display : in_data3 0000 at 113 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data3 0000 at 114 ns +Display : in_data1 0111 at 116 ns +Display : in_data2 0001 at 118 ns +Display : in_data2 0001 at 119 ns +Display : in_data2 0001 at 120 ns +Display : in_data2 0001 at 121 ns +Display : in_data2 0001 at 122 ns +Display : in_data2 0001 at 123 ns +Display : in_data3 0000 at 125 ns +Display : in_data3 0000 at 126 ns +Display : in_data3 0000 at 127 ns +Display : in_data3 0000 at 128 ns +Display : in_data3 0000 at 129 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data3 0000 at 130 ns +Display : in_data1 1000 at 132 ns +Display : in_data2 0001 at 134 ns +Display : in_data2 0001 at 135 ns +Display : in_data3 0000 at 137 ns +Display : in_data3 0000 at 138 ns +Display : in_data3 0000 at 139 ns +Display : in_data3 0000 at 140 ns +Display : in_data3 0000 at 141 ns +Display : in_data3 0000 at 142 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1001 at 148 ns +Display : in_data2 0001 at 150 ns +Display : in_data2 0001 at 151 ns +Display : in_data3 0000 at 153 ns +Display : in_data3 0000 at 154 ns +Display : in_data3 0000 at 155 ns +Display : in_data3 0000 at 156 ns +Display : in_data3 0000 at 157 ns +Display : in_data3 0000 at 158 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1010 at 164 ns +Display : in_data2 0001 at 166 ns +Display : in_data2 0001 at 167 ns +Display : in_data3 0000 at 169 ns +Display : in_data3 0000 at 170 ns +Display : in_data3 0000 at 171 ns +Display : in_data3 0000 at 172 ns +Display : in_data3 0000 at 173 ns +Display : in_data3 0000 at 174 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1011 at 180 ns +Display : in_data2 0001 at 182 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data3 0000 at 188 ns +Display : in_data3 0000 at 189 ns +Display : in_data3 0000 at 190 ns +Display : in_data3 0000 at 191 ns +Display : in_data3 0000 at 192 ns +Display : in_data3 0000 at 193 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1100 at 196 ns +Display : in_data2 0001 at 198 ns +Display : in_data2 0001 at 199 ns +Display : in_data3 0000 at 201 ns +Display : in_data3 0000 at 202 ns +Display : in_data3 0000 at 203 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1101 at 212 ns +Display : in_data2 0001 at 214 ns +Display : in_data2 0001 at 215 ns +Display : in_data3 0000 at 217 ns +Display : in_data3 0000 at 218 ns +Display : in_data3 0000 at 219 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1110 at 228 ns +Display : in_data2 0001 at 230 ns +Display : in_data2 0001 at 231 ns +Display : in_data3 0000 at 233 ns +Display : in_data3 0000 at 234 ns +Display : in_data3 0000 at 235 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1111 at 244 ns +Display : in_data2 0001 at 246 ns +Display : in_data2 0001 at 247 ns +Display : in_data3 0000 at 249 ns +Display : in_data3 0000 at 250 ns +Display : in_data3 0000 at 251 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp new file mode 100644 index 000000000..177cebdfb --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + balancing balancing1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp new file mode 100644 index 000000000..65f97f5d6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h new file mode 100644 index 000000000..a03d3e296 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp new file mode 100644 index 000000000..2d6ece6cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + + +void datatypes::entry() { + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_value4.write(0); + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + // reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //checking if condition on a range of bits + if (tmp1.range(1,3) == 4) { + out_value1.write(3); + } else if (tmp1.range(3,1) == 4) { + out_value1.write(2); + } else { + out_value1.write(tmp1); + }; + wait(); + + if (tmp2[2]) { + out_value2.write(3); + } else if ((bool)tmp1[1]==true) { + out_value2.write(2); + } else { + out_value2.write(tmp2); + }; + wait(); + + if (tmp3.range(1,3)=="000" || ((tmp3.range(3,1).to_uint()!=4) && + tmp3.range(3,1).to_uint()!=5 && tmp3.range(3,1).to_uint()!=6 && + tmp3.range(3,1).to_uint()!=7)) { + out_value3.write(1); + } else { + out_value3.write(tmp3); + }; + + if (tmp4.range(1,3)=="000" || (tmp4.range(3,1).to_uint()!=4 && + tmp4.range(3,1).to_uint()!=5 && tmp4.range(3,1).to_uint()!=6 && + tmp4.range(3,1).to_uint()!=7)) { + out_value4.write(1); + } else { + out_value4.write(tmp4); + }; + + out_valid.write(true); + wait(); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f new file mode 100644 index 000000000..c767ce1c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/datatypes.cpp +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h new file mode 100644 index 000000000..ac098dc52 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal_bool_vector& in_value4; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal_bool_vector& out_value4; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp new file mode 100644 index 000000000..530b46ce3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h new file mode 100644 index 000000000..5fcc3c5b3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log new file mode 100644 index 000000000..f183028c3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 0001 0001 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0001 0001 0001 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0011 0010 0001 0001 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0011 0010 0001 0001 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0011 0001 0001 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0011 0001 0001 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0011 0001 0001 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0011 0001 0001 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 0010 1000 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 0010 1001 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 0010 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 0010 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 0011 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 0011 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 0011 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 0011 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp new file mode 100644 index 000000000..b7e9c4496 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal_bool_vector result4; + sc_signal<bool> output_valid; + + + + datatypes datatypes1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + result3, + result4, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + result4, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp new file mode 100644 index 000000000..c3d3dea5a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h new file mode 100644 index 000000000..058da3946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp new file mode 100644 index 000000000..f089446c8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h new file mode 100644 index 000000000..f42a6b294 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp new file mode 100644 index 000000000..90972a738 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp @@ -0,0 +1,168 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" + +void fsm::entry(){ + + sc_biguint<4> tmp1; + sc_biguint<4> tmp2; + sc_biguint<4> tmp3; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + unsigned int tmpint; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + + //easy, just a bunch of different waits + out_valid1.write(true); + tmpint = tmp1.to_uint(); + wait(); + switch (tmpint) { + case 4 : + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + break; + case 3 : + out_value1.write(2); + wait(); + wait(); + wait(); + break; + case 2 : + out_value1.write(1); + wait(); + wait(); + break; + default : + out_value1.write(tmp1); + wait(); + break; + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + out_valid2.write(true); + wait(); + tmpint = tmp2.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + break; + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + wait(); + break; + case 8 : + case 9 : + case 10 : + case 11 : + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + break; + }; + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + // and just another short case, maybe later to check unbalanched case + tmp3 = in_value3.read(); + out_valid3.write(true); + wait(); + tmpint = tmp3.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp3 = tmp3*tmp3*tmp3; + wait(); + break; + default : + //short operation should not extent latency + out_tmp3 = 4; + wait(); + break; + }; + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f new file mode 100644 index 000000000..c9b315fc7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f @@ -0,0 +1,4 @@ +fsm/display.cpp +fsm/fsm.cpp +fsm/main.cpp +fsm/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h new file mode 100644 index 000000000..ee5feb351 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( fsm ) +{ + SC_HAS_PROCESS( fsm ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + fsm( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log new file mode 100644 index 000000000..89ea6bcd6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log @@ -0,0 +1,142 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data1 0000 at 5 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data3 0000 at 10 ns +Display : in_data3 0000 at 11 ns +Display : in_data3 0000 at 12 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data1 0000 at 20 ns +Display : in_data1 0001 at 21 ns +Display : in_data2 0000 at 23 ns +Display : in_data2 0000 at 24 ns +Display : in_data3 0000 at 26 ns +Display : in_data3 0000 at 27 ns +Display : in_data3 0001 at 28 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data1 0001 at 38 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data3 0001 at 43 ns +Display : in_data3 0001 at 44 ns +Display : in_data3 1000 at 45 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data1 0001 at 52 ns +Display : in_data1 0010 at 53 ns +Display : in_data1 0010 at 54 ns +Display : in_data1 0010 at 55 ns +Display : in_data2 1000 at 57 ns +Display : in_data2 1000 at 58 ns +Display : in_data3 1000 at 60 ns +Display : in_data3 1000 at 61 ns +Display : in_data3 1011 at 62 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0010 at 72 ns +Display : in_data1 0011 at 73 ns +Display : in_data2 1011 at 75 ns +Display : in_data2 1011 at 76 ns +Display : in_data3 1011 at 78 ns +Display : in_data3 1011 at 79 ns +Display : in_data3 0100 at 80 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data1 0011 at 84 ns +Display : in_data1 0101 at 85 ns +Display : in_data2 0100 at 87 ns +Display : in_data2 0100 at 88 ns +Display : in_data3 0100 at 90 ns +Display : in_data3 0100 at 91 ns +Display : in_data3 0100 at 92 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0101 at 100 ns +Display : in_data1 0110 at 101 ns +Display : in_data2 0100 at 103 ns +Display : in_data2 0100 at 104 ns +Display : in_data3 0100 at 106 ns +Display : in_data3 0100 at 107 ns +Display : in_data3 0100 at 108 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data1 0110 at 116 ns +Display : in_data1 0111 at 117 ns +Display : in_data2 0100 at 119 ns +Display : in_data2 0100 at 120 ns +Display : in_data3 0100 at 122 ns +Display : in_data3 0100 at 123 ns +Display : in_data3 0100 at 124 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data1 0111 at 132 ns +Display : in_data1 1000 at 133 ns +Display : in_data2 0100 at 135 ns +Display : in_data2 0100 at 136 ns +Display : in_data2 0100 at 137 ns +Display : in_data2 0100 at 138 ns +Display : in_data3 0100 at 140 ns +Display : in_data3 0100 at 141 ns +Display : in_data3 0100 at 142 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1000 at 148 ns +Display : in_data1 1001 at 149 ns +Display : in_data2 0001 at 151 ns +Display : in_data2 0001 at 152 ns +Display : in_data2 0001 at 153 ns +Display : in_data2 0001 at 154 ns +Display : in_data3 0100 at 156 ns +Display : in_data3 0100 at 157 ns +Display : in_data3 0100 at 158 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1001 at 164 ns +Display : in_data1 1010 at 165 ns +Display : in_data2 0001 at 167 ns +Display : in_data2 0001 at 168 ns +Display : in_data2 0001 at 169 ns +Display : in_data2 0001 at 170 ns +Display : in_data3 0100 at 172 ns +Display : in_data3 0100 at 173 ns +Display : in_data3 0100 at 174 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1010 at 180 ns +Display : in_data1 1011 at 181 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data3 0100 at 188 ns +Display : in_data3 0100 at 189 ns +Display : in_data3 0100 at 190 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1011 at 196 ns +Display : in_data1 1100 at 197 ns +Display : in_data2 0001 at 199 ns +Display : in_data3 0100 at 201 ns +Display : in_data3 0100 at 202 ns +Display : in_data3 0100 at 203 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1100 at 212 ns +Display : in_data1 1101 at 213 ns +Display : in_data2 0001 at 215 ns +Display : in_data3 0100 at 217 ns +Display : in_data3 0100 at 218 ns +Display : in_data3 0100 at 219 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1101 at 228 ns +Display : in_data1 1110 at 229 ns +Display : in_data2 0001 at 231 ns +Display : in_data3 0100 at 233 ns +Display : in_data3 0100 at 234 ns +Display : in_data3 0100 at 235 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1110 at 244 ns +Display : in_data1 1111 at 245 ns +Display : in_data2 0001 at 247 ns +Display : in_data3 0100 at 249 ns +Display : in_data3 0100 at 250 ns +Display : in_data3 0100 at 251 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp new file mode 100644 index 000000000..5280ddd17 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + fsm fsm1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp new file mode 100644 index 000000000..65f97f5d6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h new file mode 100644 index 000000000..a03d3e296 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp new file mode 100644 index 000000000..0135a0381 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h new file mode 100644 index 000000000..74d4c67ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log new file mode 100644 index 000000000..3a3a8c358 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0000 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0000 0010 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0000 0011 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0100 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0101 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0110 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0111 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp new file mode 100644 index 000000000..08da0e3ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" + +// list of defines +#define clock(a) wait(a) +#define intu4(a) sc_biguint<4> a; +#define vec4(a) sc_lv<4> a; +#define my_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + break; \ + default : \ + b = c; \ + break; \ + }; +#define my_wait_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + wait(); \ + break; \ + default : \ + b = c; \ + wait(); \ + break; \ + }; + +void inlining::entry(){ + + int tmp1; + int tmp2; + vec4(tmp3); + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_valid.write(false); + clock(1); + } else clock(1); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read().to_int(); + tmp2 = in_value2.read().to_int(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //execution + my_wait_case(tmp1, tmp3, tmp4); + out_value1.write(tmp3); + clock(1); + + my_case(tmp2, tmp3, tmp4); + out_value2.write(tmp4); + out_valid.write(true); + clock(1); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f new file mode 100644 index 000000000..fc00870e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f @@ -0,0 +1,4 @@ +inlining/display.cpp +inlining/inlining.cpp +inlining/main.cpp +inlining/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h new file mode 100644 index 000000000..70380e24e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h @@ -0,0 +1,93 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( inlining ) +{ + SC_HAS_PROCESS( inlining ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1 ; + const sc_signal_bool_vector& in_value2 ; + const sc_signal_bool_vector& in_value3 ; + const sc_signal_bool_vector& in_value4 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + inlining( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + // + void entry (); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp new file mode 100644 index 000000000..c859cafce --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal<bool> output_valid; + + + + inlining inlining1 ( + "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid + ); + + display display1 ("display", + clock, + result1, + result2, + output_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp new file mode 100644 index 000000000..c3d3dea5a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h new file mode 100644 index 000000000..058da3946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF |